__projnav.log

结合XILINXCPLD所做的模拟RS232通信verilog源程序

ISE Auto-Make Log File
-----------------------

Starting: 'jhdparse @_send.jp'


JHDPARSE - VHDL/Verilog Parser.
ISE 4.1i Copyright(c) 1999-2001 Xilinx, Inc.  All rights reserved. 

Scanning    d:/Xilinx_WebPACK/data/simprim.lst
Scanning    d:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v
Scanning    send.v
Writing send.jhd.

JHDPARSE complete -    0 errors,    0 warnings.

Done: completed successfully.

ISE Auto-Make Log File
-----------------------

Starting: 'jhdparse @_send.jp'


JHDPARSE - VHDL/Verilog Parser.
ISE 4.1i Copyright(c) 1999-2001 Xilinx, Inc.  All rights reserved. 

Scanning    d:/Xilinx_WebPACK/data/simprim.lst
Scanning    d:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v
Scanning    send.v
Writing send.jhd.

JHDPARSE complete -    0 errors,    0 warnings.

Done: completed successfully.

ISE Auto-Make Log File
-----------------------

Updating: Assign Pins (ChipViewer)

Starting: 'exewrap @__send_2prj_exewrap.rsp'


Creating TCL Process
Done: completed successfully.

Starting: 'exewrap -mode pipe -tapkeep -command D:/Xilinx_WebPACK/bin/nt/xst.exe -ifn send.xst -ofn send.syr'


Starting: 'D:/Xilinx_WebPACK/bin/nt/xst.exe -ifn send.xst -ofn send.syr '


Release 4.1WP3.x - xst E.33
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to .
CPU : 0.00 / 0.22 s | Elapsed : 0.00 / 0.00 s
 
--> Parameter overwrite set to YES
CPU : 0.00 / 0.22 s | Elapsed : 0.00 / 0.00 s
 
--> =========================================================================
---- Source Parameters
Input Format                       : VERILOG
Input File Name                    : send.prj

---- Target Parameters
Target Device                      : XC9500
Output File Name                   : send
Output Format                      : NGC
Target Technology                  : 9500

---- Source Options
Top Module Name                    : send
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Flip-Flop Type                 : D
Mux Extraction                     : YES
Resource Sharing                   : YES
Complex Clock Enable Extraction    : YES

---- Target Options
Add IO Buffers                     : YES
Equivalent register Removal        : YES
Macro Generator                    : Auto
MACRO Preserve                     : YES
XOR Preserve                       : YES

---- General Options
Optimization Criterion             : Speed
Optimization Effort                : 1
Check Attribute Syntax             : YES
Keep Hierarchy                     : YES

---- Other Options
wysiwyg                            : NO

=========================================================================

 
Compiling source file : send.prj
Compiling included source file 'send.v'
Module <send> compiled.
Continuing compilation of source file 'send.prj'
Compiling included source file 'd:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v'
Continuing compilation of source file 'send.prj'
No errors in compilation
Analysis of file <send.prj> succeeded.
 
 
Starting Verilog synthesis.
 
Analyzing top module <send>.
Module <send> is correct for synthesis.

Synthesizing Unit <send>.
    Related source file is send.v.
WARNING:Xst:737 - Found 8-bit latch for signal <uart_buf>.
    Found 11-bit comparator less for signal <$n0001> created at line 16.
    Found 4-bit comparator less for signal <$n0006> created at line 52.
    Found 4-bit adder for signal <$n0017> created at line 53.
    Found 1-bit register for signal <bit_start>.
    Found 4-bit register for signal <bitcnt_reg>.
    Found 11-bit up counter for signal <count>.
    Found 1-bit register for signal <txd_reg>.
    Summary:
	inferred   1 Counter(s).
	inferred   6 D-type flip-flop(s).
	inferred   8 Latch(s).
	inferred   1 Adder/Subtracter(s).
	inferred   2 Comparator(s).
Unit <send> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 3
  4-bit register                   : 1
  1-bit register                   : 2
# Latches                          : 1
  8-bit latch                      : 1
# Counters                         : 1
  11-bit up counter                : 1
# Adders/Subtractors               : 1
  4-bit adder                      : 1
# Comparators                      : 2
  11-bit comparator less           : 1
  4-bit comparator less            : 1

=========================================================================


Starting low level synthesis...

Optimizing unit <send> ...
=========================================================================
Final Results
Output File Name                   : send
Output Format                      : NGC
Optimization Criterion             : Speed
Target Technology                  : 9500
Keep Hierarchy                     : YES
Macro Preserve                     : YES
Macro Generation                   : Auto
XOR Preserve                       : YES

Macro Statistics
# Comparators                      : 2
  11-bit comparator less           : 1
  4-bit comparator less            : 1
# Xors                             : 13
  1-bit xor2                       : 13

Design Statistics
# Edif Instances                   : 147
# I/Os                             : 10

=========================================================================
CPU : 2.30 / 2.52 s | Elapsed : 3.00 / 3.00 s
 
--> 
EXEWRAP detected that program 'D:/Xilinx_WebPACK/bin/nt/xst.exe' completed successfully.

Done: completed successfully.

Starting: 'exewrap -tapkeep -mode pipe -tcl -command d:/Xilinx_WebPACK/data/projnav/_edfTOngd.tcl _ngdbld.rsp send ngdbuild.rsp'


Creating TCL Process
Starting: 'ngdbuild -f ngdbuild.rsp'


Release 4.1WP3.x - ngdbuild E.33
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.

Command Line: ngdbuild -dd _ngo -uc send.ucf -p XC9500 send.ngc send.ngd 

Reading NGO file "C:/WINDOWS/Desktop/send/send.ngc" ...
Reading component libraries for design expansion...
Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_1"...
WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_1 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_10"...
WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_10 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_M
xor_Result_2"...
WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_2 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_M
xor_Result_3"...
WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_3 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_M
xor_Result_4"...
WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_4 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_M
xor_Result_5"...
WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_5 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_M
xor_Result_6"...
WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_6 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_M
xor_Result_7"...
WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_7 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_8"...
WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_8 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_M
xor_Result_9"...
WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_9 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__n0017_Mxor_Re
sult_1"...
WARNING:LBEngine:353 - Module Madd__n0017_Mxor_Result_1 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__n0017_Mxor_Re
sult_2"...
WARNING:LBEngine:353 - Module Madd__n0017_Mxor_Result_2 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__n0017_Mxor_Re
sult_3"...
WARNING:LBEngine:353 - Module Madd__n0017_Mxor_Result_3 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.
Annotating constraints to design from file "send.ucf" ...

Checking timing specifications ...

Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "send.ngd" ...

Writing NGDBUILD log file "send.bld"...

NGDBUILD done.
Tcl d:/Xilinx_WebPACK/data/projnav/_edfTOngd.tcl detected that program 'ngdbuild -f ngdbuild.rsp' completed successfully.




Done: completed successfully.

Starting: 'exewrap -mode pipe -tapkeep -tcl -command _chipview.tcl'


Creating TCL Process
Starting: 'ChipView.bat -f send.ngd -uc send.ucf -dev XC95108-7-PC84'


Tcl _chipview.tcl detected that program 'ChipView.bat -f send.ngd -uc send.ucf -dev XC95108-7-PC84' completed successfully.




Starting: 'chkdate'


Tcl _chipview.tcl detected that program 'chkdate' completed successfully.

Existing implementation results (if any) will be retained.

Done: completed successfully.

ISE Auto-Make Log File
-----------------------

Starting: 'jhdparse @_send.jp'


JHDPARSE - VHDL/Verilog Parser.
ISE 4.1i Copyright(c) 1999-2001 Xilinx, Inc.  All rights reserved. 

Scanning    d:/Xilinx_WebPACK/data/simprim.lst
Scanning    d:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v
Scanning    send.v
Writing send.jhd.

JHDPARSE complete -    0 errors,    0 warnings.

Done: completed successfully.