📄 send.rpt
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count_10 2 0 0 3 FB2_8 STD 76 GTS/I/O (b)
count_0 2 0 0 3 FB2_9 STD 77 GTS/I/O (b)
bit_start 2 0 0 3 FB2_10 STD (b) (b)
uart_buf_1 2 0 0 3 FB2_11 STD 79 I/O (b)
uart_buf_0 2 0 0 3 FB2_12 STD 80 I/O (b)
count_7 3 0 0 2 FB2_13 STD (b) (b)
count_1 4 0 0 1 FB2_14 STD 81 I/O (b)
count_6 5 0 0 0 FB2_15 STD 82 I/O (b)
count_5 5 0 0 0 FB2_16 STD 83 I/O (b)
count_4 5 0 0 0 FB2_17 STD 84 I/O (b)
count_3 5 0 0 0 FB2_18 STD (b) (b)
Signals Used by Logic in Function Block
1: count_0.FBK.LFBK 7: count_5.FBK.LFBK 12: "uart_buf_0/uart_buf_0_SETF"
2: count_1.FBK.LFBK 8: count_6.FBK.LFBK 13: "uart_buf_1/uart_buf_1_RSTF"
3: count_10.FBK.LFBK 9: count_7.FBK.LFBK 14: "uart_buf_1/uart_buf_1_SETF"
4: count_2 10: count_8.FBK.LFBK 15: "uart_buf_5/uart_buf_5_RSTF"
5: count_3.FBK.LFBK 11: count_9.FBK.LFBK 16: "uart_buf_7/uart_buf_7_RSTF"
6: count_4.FBK.LFBK
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
uart_buf_6 ...............X........................ 1 1
uart_buf_5 ..............X......................... 1 1
uart_buf_4 ...............X........................ 1 1
count_9 XXXXXXXXXXX............................. 11 11
count_8 XXXXXXXXXX.............................. 10 10
count_10 XXXXXXXXXXX............................. 11 11
count_0 X.X.....XXX............................. 5 5
bit_start ..X.....XXX............................. 4 4
uart_buf_1 ............XX.......................... 2 2
uart_buf_0 ...........X..X......................... 2 2
count_7 XXXXXXXXXXX............................. 11 11
count_1 XXX.....XXX............................. 6 6
count_6 XXXXXXXXXXX............................. 11 11
count_5 XXXXXXX.XXX............................. 10 10
count_4 XXXXXX..XXX............................. 9 9
count_3 XXXXX...XXX............................. 8 8
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 1/35
Number of signals used by logic mapping into function block: 1
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB3_1 (b)
(unused) 0 0 0 5 FB3_2 14 I/O
(unused) 0 0 0 5 FB3_3 15 I/O
(unused) 0 0 0 5 FB3_4 (b)
(unused) 0 0 0 5 FB3_5 17 I/O
(unused) 0 0 0 5 FB3_6 18 I/O
(unused) 0 0 0 5 FB3_7 (b)
(unused) 0 0 0 5 FB3_8 19 I/O
(unused) 0 0 0 5 FB3_9 20 I/O
(unused) 0 0 0 5 FB3_10 (b)
(unused) 0 0 0 5 FB3_11 21 I/O
(unused) 0 0 0 5 FB3_12 23 I/O
(unused) 0 0 0 5 FB3_13 (b)
(unused) 0 0 0 5 FB3_14 24 I/O
(unused) 0 0 0 5 FB3_15 25 I/O
(unused) 0 0 0 5 FB3_16 26 I/O
(unused) 0 0 0 5 FB3_17 31 I/O
uart_buf_7 1 0 0 4 FB3_18 STD (b) (b)
Signals Used by Logic in Function Block
1: "uart_buf_7/uart_buf_7_RSTF"
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
uart_buf_7 X....................................... 1 1
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 0/36
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB4_1 (b)
(unused) 0 0 0 5 FB4_2 57 I/O I
(unused) 0 0 0 5 FB4_3 58 I/O I
(unused) 0 0 0 5 FB4_4 (b)
(unused) 0 0 0 5 FB4_5 61 I/O I
(unused) 0 0 0 5 FB4_6 62 I/O I
(unused) 0 0 0 5 FB4_7 (b)
(unused) 0 0 0 5 FB4_8 63 I/O I
(unused) 0 0 0 5 FB4_9 65 I/O
(unused) 0 0 0 5 FB4_10 (b)
(unused) 0 0 0 5 FB4_11 66 I/O
(unused) 0 0 0 5 FB4_12 67 I/O
(unused) 0 0 0 5 FB4_13 (b)
(unused) 0 0 0 5 FB4_14 68 I/O
(unused) 0 0 0 5 FB4_15 69 I/O
(unused) 0 0 0 5 FB4_16 (b)
(unused) 0 0 0 5 FB4_17 70 I/O
(unused) 0 0 0 5 FB4_18 (b)
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB5 ***********************************
Number of function block inputs used/remaining: 0/36
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB5_1 (b)
(unused) 0 0 0 5 FB5_2 32 I/O
(unused) 0 0 0 5 FB5_3 33 I/O
(unused) 0 0 0 5 FB5_4 (b)
(unused) 0 0 0 5 FB5_5 34 I/O
(unused) 0 0 0 5 FB5_6 35 I/O
(unused) 0 0 0 5 FB5_7 (b)
(unused) 0 0 0 5 FB5_8 36 I/O
(unused) 0 0 0 5 FB5_9 37 I/O
(unused) 0 0 0 5 FB5_10 (b)
(unused) 0 0 0 5 FB5_11 39 I/O
(unused) 0 0 0 5 FB5_12 40 I/O
(unused) 0 0 0 5 FB5_13 (b)
(unused) 0 0 0 5 FB5_14 41 I/O
(unused) 0 0 0 5 FB5_15 43 I/O
(unused) 0 0 0 5 FB5_16 (b)
(unused) 0 0 0 5 FB5_17 44 I/O
(unused) 0 0 0 5 FB5_18 (b)
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB6 ***********************************
Number of function block inputs used/remaining: 0/36
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB6_1 (b)
(unused) 0 0 0 5 FB6_2 45 I/O
(unused) 0 0 0 5 FB6_3 46 I/O
(unused) 0 0 0 5 FB6_4 (b)
(unused) 0 0 0 5 FB6_5 47 I/O
(unused) 0 0 0 5 FB6_6 48 I/O
(unused) 0 0 0 5 FB6_7 (b)
(unused) 0 0 0 5 FB6_8 50 I/O
(unused) 0 0 0 5 FB6_9 51 I/O
(unused) 0 0 0 5 FB6_10 (b)
(unused) 0 0 0 5 FB6_11 52 I/O
(unused) 0 0 0 5 FB6_12 53 I/O
(unused) 0 0 0 5 FB6_13 (b)
(unused) 0 0 0 5 FB6_14 54 I/O I
(unused) 0 0 0 5 FB6_15 55 I/O I
(unused) 0 0 0 5 FB6_16 (b)
(unused) 0 0 0 5 FB6_17 56 I/O I
(unused) 0 0 0 5 FB6_18 (b)
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
"$OpTx$FX_DC$21" = "key_send<0>" * "key_send<1>" * "key_send<2>" *
/"key_send<7>"
+ "key_send<0>" * /"key_send<1>" * "key_send<2>" *
"key_send<7>"
+ /"key_send<0>" * "key_send<1>" * "key_send<2>" *
"key_send<7>"
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