📄 send.rpt
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cpldfit: version E.33 Xilinx Inc.
Fitter Report
Design Name: send Date: 11-26-2002, 9:31AM
Device Used: XC95108-7-PC84
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
33 /108 ( 30%) 124 /540 ( 22%) 25 /108 ( 23%) 10 /69 ( 14%) 48 /216 ( 22%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 8 8 | I/O : 9 54
Output : 1 1 | GCK/IO : 1 2
Bidirectional : 0 0 | GTS/IO : 0 2
GCK : 1 1 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 10 10
MACROCELL RESOURCES:
Total Macrocells Available 108
Registered Macrocells 25
Non-registered Macrocell driving I/O 0
GLOBAL RESOURCES:
Signal 'clock' mapped onto global clock net GCK1.
Global output enable net(s) unused.
Global set/reset net(s) unused.
POWER DATA:
There are 33 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 33 macrocells used (MC).
End of Resource Summary
**************************** Errors and Warnings *************************
WARNING:Cpld - Signal 'uart_buf_7.SETF' has been minimized to 'GND'.
The signal is removed.
WARNING:Cpld - Signal 'uart_buf_5.SETF' has been minimized to 'GND'.
The signal is removed.
WARNING:Cpld - Signal 'uart_buf_4.SETF' has been minimized to 'GND'.
The signal is removed.
WARNING:Cpld - Signal 'uart_buf_6.RSTF' has been minimized to 'GND'.
The signal is removed.
***************Resources Used by Successfully Mapped Logic******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin
Name Pt Used Mode Rate # Type Use
$OpTx$FX_DC$21 4 4 FB1_12 STD 9 GCK/I/O GCK
$OpTx$FX_DC$22 4 4 FB1_11 STD 7 I/O (b)
bit_start 2 4 FB2_10 STD (b) (b)
bitcnt_reg_0 5 13 FB1_14 STD 10 GCK/I/O (b)
bitcnt_reg_1 4 5 FB1_10 STD (b) (b)
bitcnt_reg_2 3 5 FB1_1 STD (b) (b)
bitcnt_reg_3 4 13 FB1_9 STD 6 I/O (b)
count_0 2 5 FB2_9 STD 77 GTS/I/O (b)
count_1 4 6 FB2_14 STD 81 I/O (b)
count_10 2 11 FB2_8 STD 76 GTS/I/O (b)
count_2 5 7 FB1_13 STD (b) (b)
count_3 5 8 FB2_18 STD (b) (b)
count_4 5 9 FB2_17 STD 84 I/O (b)
count_5 5 10 FB2_16 STD 83 I/O (b)
count_6 5 11 FB2_15 STD 82 I/O (b)
count_7 3 11 FB2_13 STD (b) (b)
count_8 2 10 FB2_7 STD (b) (b)
count_9 2 11 FB2_6 STD 75 I/O (b)
txd 11 21 FB1_3 STD FAST 2 I/O O
uart_buf_0 2 2 FB2_12 STD 80 I/O (b)
uart_buf_0/uart_buf_0_SETF 4 8 FB1_8 STD 5 I/O (b)
uart_buf_1 2 2 FB2_11 STD 79 I/O (b)
uart_buf_1/uart_buf_1_RSTF 4 8 FB1_7 STD (b) (b)
uart_buf_1/uart_buf_1_SETF 4 8 FB1_6 STD 4 I/O (b)
uart_buf_2 2 10 FB1_5 STD 3 I/O (b)
uart_buf_3 2 9 FB1_4 STD (b) (b)
uart_buf_3/uart_buf_3_RSTF 7 8 FB1_15 STD 11 I/O (b)
uart_buf_4 1 1 FB2_5 STD 74 GSR/I/O (b)
uart_buf_5 1 1 FB2_4 STD (b) (b)
uart_buf_5/uart_buf_5_RSTF 8 8 FB1_18 STD (b) (b)
uart_buf_6 1 1 FB2_3 STD 72 I/O (b)
uart_buf_7 1 1 FB3_18 STD (b) (b)
uart_buf_7/uart_buf_7_RSTF 8 8 FB1_17 STD 13 I/O (b)
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
clock FB1_12 9 GCK/I/O GCK
key_send<0> FB6_14 54 I/O I
key_send<1> FB6_15 55 I/O I
key_send<2> FB6_17 56 I/O I
key_send<3> FB4_2 57 I/O I
key_send<4> FB4_3 58 I/O I
key_send<5> FB4_5 61 I/O I
key_send<6> FB4_6 62 I/O I
key_send<7> FB4_8 63 I/O I
End of Resources Used by Successfully Mapped Logic
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 16 31 31 79 1/0 12
FB2 16 16 16 44 0/0 12
FB3 1 1 1 1 0/0 12
FB4 0 0 0 0 0/0 11
FB5 0 0 0 0 0/0 11
FB6 0 0 0 0 0/0 11
---- ----- ----- -----
33 124 1/0 69
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 31/5
Number of signals used by logic mapping into function block: 31
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
bitcnt_reg_2 3 0 /\2 0 FB1_1 STD (b) (b)
(unused) 0 0 \/5 0 FB1_2 1 I/O (b)
txd 11 6<- 0 0 FB1_3 STD 2 I/O O
uart_buf_3 2 0 /\1 2 FB1_4 STD (b) (b)
uart_buf_2 2 0 0 3 FB1_5 STD 3 I/O (b)
uart_buf_1/uart_buf_1_SETF
4 0 0 1 FB1_6 STD 4 I/O (b)
uart_buf_1/uart_buf_1_RSTF
4 0 0 1 FB1_7 STD (b) (b)
uart_buf_0/uart_buf_0_SETF
4 0 0 1 FB1_8 STD 5 I/O (b)
bitcnt_reg_3 4 0 0 1 FB1_9 STD 6 I/O (b)
bitcnt_reg_1 4 0 0 1 FB1_10 STD (b) (b)
$OpTx$FX_DC$22 4 0 \/1 0 FB1_11 STD 7 I/O (b)
$OpTx$FX_DC$21 4 1<- \/2 0 FB1_12 STD 9 GCK/I/O GCK
count_2 5 2<- \/2 0 FB1_13 STD (b) (b)
bitcnt_reg_0 5 2<- \/2 0 FB1_14 STD 10 GCK/I/O (b)
uart_buf_3/uart_buf_3_RSTF
7 2<- 0 0 FB1_15 STD 11 I/O (b)
(unused) 0 0 \/4 1 FB1_16 12 GCK/I/O (b)
uart_buf_7/uart_buf_7_RSTF
8 4<- \/1 0 FB1_17 STD 13 I/O (b)
uart_buf_5/uart_buf_5_RSTF
8 3<- 0 0 FB1_18 STD (b) (b)
Signals Used by Logic in Function Block
1: "$OpTx$FX_DC$21.FBK".LFBK
12: bitcnt_reg_0.FBK.LFBK
22: count_9
2: "$OpTx$FX_DC$22.FBK".LFBK
13: bitcnt_reg_1.FBK.LFBK
23: uart_buf_0
3: "key_send<7>" 14: bitcnt_reg_2.FBK.LFBK
24: uart_buf_1
4: "key_send<0>" 15: bitcnt_reg_3.FBK.LFBK
25: uart_buf_2.FBK.LFBK
5: "key_send<1>" 16: count_0 26: uart_buf_3.FBK.LFBK
6: "key_send<2>" 17: count_1 27: "uart_buf_3/uart_buf_3_RSTF.FBK".LFBK
7: "key_send<3>" 18: count_10 28: uart_buf_4
8: "key_send<4>" 19: count_2.FBK.LFBK 29: uart_buf_5
9: "key_send<5>" 20: count_7 30: uart_buf_6
10: "key_send<6>" 21: count_8 31: uart_buf_7
11: bit_start
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
bitcnt_reg_2 ..........XXXXX......................... 5 5
txd ..XXXXXXXXXXXXX.......XXXX.XXXX......... 21 21
uart_buf_3 ..XXXXXXXX................X............. 9 9
uart_buf_2 XXXXXXXXXX.............................. 10 10
uart_buf_1/uart_buf_1_SETF
..XXXXXXXX.............................. 8 8
uart_buf_1/uart_buf_1_RSTF
..XXXXXXXX.............................. 8 8
uart_buf_0/uart_buf_0_SETF
..XXXXXXXX.............................. 8 8
bitcnt_reg_3 ..XXXXXXXXXXXXX......................... 13 13
bitcnt_reg_1 ..........XXXXX......................... 5 5
$OpTx$FX_DC$22 ......XXXX.............................. 4 4
$OpTx$FX_DC$21 ..XXXX.................................. 4 4
count_2 ...............XXXXXXX.................. 7 7
bitcnt_reg_0 ..XXXXXXXXXXXXX......................... 13 13
uart_buf_3/uart_buf_3_RSTF
..XXXXXXXX.............................. 8 8
uart_buf_7/uart_buf_7_RSTF
..XXXXXXXX.............................. 8 8
uart_buf_5/uart_buf_5_RSTF
..XXXXXXXX.............................. 8 8
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 16/20
Number of signals used by logic mapping into function block: 16
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB2_1 (b)
(unused) 0 0 0 5 FB2_2 71 I/O
uart_buf_6 1 0 0 4 FB2_3 STD 72 I/O (b)
uart_buf_5 1 0 0 4 FB2_4 STD (b) (b)
uart_buf_4 1 0 0 4 FB2_5 STD 74 GSR/I/O (b)
count_9 2 0 0 3 FB2_6 STD 75 I/O (b)
count_8 2 0 0 3 FB2_7 STD (b) (b)
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