sap_1_tb_runtest.do

這是用verilog寫的一個簡單的處理器

--* This automatically generated file is a part of Verilog testbench.
--*   This file was generated by Active-HDL 4.1 (TB_verilog v.1.1).
--*   Copyright (C) ALDEC Inc.
--* This MACRO file contains the set of commands initializes the Test Bench simulation
--* and is a part of Verilog Testbench for module "SAP_1"
--* This file was generated on: Wed Jun  1 17:54:05 2005

SetActiveLib -work
#Compiling UUT module design files
comp $DSN\src\SAP_1.v
comp $DSN\src\TestBench\SAP_1_TB.v
vsim SAP_1_tb

wave
wave asy_rst
wave clk
wave Oreg
wave go

run

#End simulation macro