1.mgf

這是用verilog寫的一個簡單的處理器

I 000036 22 1637 1117624478868 PROM
(_unit VERILOG 1.152.1.136 (PROM 0 1 (PROM 0 1 ))
	(_version v27)
	(_time 1117624478507 2005.06.01 19:14:38)
	(_source (\.\\src\\prom.v\))
	(_use (std(standard))(vl(verilog_logic)))
	(_entity
		(_time 1117624478507)
		(_use )
	)
	(_object
		(_type (_internal ~[3:0]wire~ 0 1 (_array ~wire ((_downto (i 3) (i 0))))))
		(_port (_internal ADDR ~[3:0]wire~ 0 1 (_architecture (_in ))) (_net  ) (_simple))
		(_type (_internal ~[7:0]reg~ 0 1 (_array ~reg ((_downto (i 7) (i 0))))))
		(_port (_internal DATA ~[7:0]reg~ 0 1 (_architecture (_out ))) (_reg ) (_simple))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (std standard real)))
		(_type (_external ~realtime (std standard real)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ALWAYS#9_0 (_architecture 0 0 9 (_process (_target(1))(_read)(_sensitivity(0)))))
		)
	)
	(_model . PROM 2 -1)

)
I 000037 22 4726 1117624597520 SAP_1
(_unit VERILOG 1.152.1.136 (SAP_1 0 28 (SAP_1 0 28 ))
	(_version v27)
	(_time 1117624596938 2005.06.01 19:16:36)
	(_source (\.\\src\\SAP_1.v\))
	(_use (std(standard))(vl(verilog_logic)))
	(_entity
		(_time 1117624596938)
		(_use )
	)
	(_object
		(_port (_internal asy_rst ~wire 0 28 (_architecture (_in ))) (_net  ) (_simple))
		(_port (_internal clk ~wire 0 28 (_architecture (_in ))) (_net  ) (_simple))
		(_type (_internal ~[7:0]reg~ 0 28 (_array ~reg ((_downto (i 7) (i 0))))))
		(_port (_internal Oreg ~[7:0]reg~ 0 28 (_architecture (_out ))) (_reg ) (_simple))
		(_port (_internal go ~wire 0 28 (_architecture (_in ))) (_net  ) (_simple))
		(_type (_internal ~[3:0]wire~ 0 34 (_array ~wire ((_downto (i 3) (i 0))))))
		(_signal (_internal OPCO ~[3:0]wire~ 0 34 (_architecture (_uni ))) (_net  ))
		(_signal (_internal CP ~reg 0 43 (_architecture (_uni ))) (_reg ) (_simple))
		(_signal (_internal CLRP ~reg 0 43 (_architecture (_uni ))) (_reg ) (_simple))
		(_signal (_internal LPC_MAR ~reg 0 43 (_architecture (_uni ))) (_reg ) (_simple))
		(_signal (_internal LIR_MAR ~reg 0 43 (_architecture (_uni ))) (_reg ) (_simple))
		(_signal (_internal LPROM_ACC ~reg 0 43 (_architecture (_uni ))) (_reg ) (_simple))
		(_signal (_internal LALU_ACC ~reg 0 43 (_architecture (_uni ))) (_reg ) (_simple))
		(_signal (_internal LPROM_B ~reg 0 43 (_architecture (_uni ))) (_reg ) (_simple))
		(_signal (_internal LPROM_IR ~reg 0 43 (_architecture (_uni ))) (_reg ) (_simple))
		(_signal (_internal LACC_O ~reg 0 43 (_architecture (_uni ))) (_reg ) (_simple))
		(_type (_internal ~[2:0]reg~ 0 45 (_array ~reg ((_downto (i 2) (i 0))))))
		(_signal (_internal state ~[2:0]reg~ 0 45 (_architecture (_uni ))) (_reg ))
		(_signal (_internal next_state ~[2:0]reg~ 0 45 (_architecture (_uni ))) (_reg ) (_simple))
		(_type (_internal ~[3:0]reg~ 0 47 (_array ~reg ((_downto (i 3) (i 0))))))
		(_signal (_internal PC ~[3:0]reg~ 0 47 (_architecture (_uni ))) (_reg ))
		(_type (_internal ~[7:0]wire~ 0 48 (_array ~wire ((_downto (i 7) (i 0))))))
		(_signal (_internal WBUS ~[7:0]wire~ 0 48 (_architecture (_uni ))) (_net  ) (_simple))
		(_signal (_internal MAR ~[3:0]reg~ 0 49 (_architecture (_uni ))) (_reg ))
		(_signal (_internal PROMO ~[7:0]wire~ 0 50 (_architecture (_uni ))) (_net  ))
		(_signal (_internal IR ~[7:0]reg~ 0 51 (_architecture (_uni ))) (_reg ))
		(_signal (_internal ACC ~[7:0]reg~ 0 52 (_architecture (_uni ))) (_reg ))
		(_signal (_internal B ~[7:0]reg~ 0 53 (_architecture (_uni ))) (_reg ))
		(_signal (_internal ALUO ~[7:0]wire~ 0 54 (_architecture (_uni ))) (_net  ))
		(_signal (_internal ALUMUX ~[3:0]reg~ 0 55 (_architecture (_uni ))) (_reg ) (_simple))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (std standard real)))
		(_type (_external ~realtime (std standard real)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#ALWAYS#58_0 (_architecture 0 0 58 (_process (_target(14))(_read(1)(0)(15)))))
			(#ALWAYS#66_1 (_architecture 1 0 66 (_process (_target(5)(6)(7)(8)(12)(9)(10)(11)(13)(24)(15))(_read)(_sensitivity(14)(4)(3)))))
			(#ALWAYS#205_2 (_architecture 2 0 205 (_process (_target(16))(_read(1)(5)(16)(6)))))
			(#ALWAYS#215_3 (_architecture 3 0 215 (_process (_target(18))(_read(1)(7)(16)(8)(20(d_3_0))))))
			(#ALWAYS#224_4 (_architecture 4 0 224 (_process (_target(20))(_read(1)(12)(19)))))
			(#ASSIGN#229_5 (_architecture 5 0 229 (_process (_alias ((OPCO)(IR(d_7_4))))(_target(4))(_sensitivity(20(d_7_4))))))
			(#ALWAYS#232_6 (_architecture 6 0 232 (_process (_target(21))(_read(1)(9)(19)(10)(23)))))
			(#ASSIGN#248_7 (_architecture 7 0 248 (_process (_target(23))(_sensitivity(24)(21)(22)(19)))))
			(#ALWAYS#250_8 (_architecture 8 0 250 (_process (_target(22))(_read(1)(11)(19)))))
			(#ALWAYS#254_9 (_architecture 9 0 254 (_process (_target(2))(_read(1)(13)(21)))))
		)
	)
	(_scope
	)
	(_instantiation prom 0 222 (_entity . PROM)
		(_port
			((MAR))
			((PROMO))
		)
	)
	(_model . SAP_1 11 -1)

)
I 000040 22 1972 1117624386275 SAP_1_tb
(_unit VERILOG 1.152.1.136 (SAP_1_tb 0 9 (SAP_1_tb 0 9 ))
	(_version v27)
	(_time 1117624385934 2005.06.01 19:13:05)
	(_source (\.\\src\\TestBench\\SAP_1_TB.v\))
	(_use (std(standard))(vl(verilog_logic)))
	(_entity
		(_time 1117624385934)
		(_use )
	)
	(_timescale 1ns 100ps)
	(_object
		(_signal (_internal asy_rst ~reg 0 13 (_architecture (_uni ))) (_reg ) (_simple))
		(_signal (_internal clk ~reg 0 14 (_architecture (_uni ))) (_reg ) (_simple))
		(_type (_internal ~[7:0]wire~ 0 15 (_array ~wire ((_downto (i 7) (i 0))))))
		(_signal (_internal Oreg ~[7:0]wire~ 0 15 (_architecture (_uni ))) (_net  ) (_simple))
		(_signal (_internal go ~reg 0 16 (_architecture (_uni ))) (_reg ) (_simple))
		(_subprogram
			

		)
		(_type (_external ~wire (vl verilog_logic wire)))
		(_type (_external ~reg (vl verilog_logic reg)))
		(_type (_external ~wand (vl verilog_logic wand)))
		(_type (_external ~wor (vl verilog_logic wor)))
		(_type (_external ~tri1 (vl verilog_logic tri1)))
		(_type (_external ~tri0 (vl verilog_logic tri0)))
		(_type (_external ~trireg (vl verilog_logic trireg)))
		(_type (_external ~supply0 (vl verilog_logic supply0)))
		(_type (_external ~supply1 (vl verilog_logic supply1)))
		(_type (_external ~real (std standard real)))
		(_type (_external ~realtime (std standard real)))
		(_type (_external ~tri (vl verilog_logic tri)))
		(_type (_external ~triand (vl verilog_logic triand)))
		(_type (_external ~trior (vl verilog_logic trior)))
		(_type (_external ~bit (vl verilog_logic bit)))
		(_type (_external ~extstd.standard.integer (std standard integer)))
		(_type (_external ~extstd.standard.bit (std standard bit)))
		(_process
			(#INITIAL#27_0 (_architecture 0 0 27 (_process (_target(0)(3)))))
			(#ALWAYS#38_1 (_architecture 1 0 38 (_process (_target(1)))))
		)
	)
	(_scope
	)
	(_instantiation UUT 0 25 (_entity . SAP_1)
		(_port
			((asy_rst) (asy_rst))
			((clk) (clk))
			((Oreg) (Oreg))
			((go) (go))
		)
	)
	(_model . SAP_1_tb 3 -1)

)
I 000037 22 4832 1117625125207 SAP_1
(_unit VERILOG 1.152.1.136 (SAP_1 0 28 (SAP_1 0 28 ))
	(_version v27)
	(_time 1117625124817 2005.06.01 19:25:24)
	(_source (\.\\src\\SAP_1.v\))
	(_use (std(standard))(vl(verilog_logic)))
	(_entity
		(_time 1117625124817)
		(_use )
	)
	(_object
		(_port (_internal asy_rst ~wire 0 28 (_architecture (_in ))) (_net  ) (_simple))
		(_port (_internal clk ~wire 0 28 (_architecture (_in ))) (_net  ) (_simple))
		(_type (_internal ~[7:0]reg~ 0 28 (_array ~reg ((_downto (i 7) (i 0))))))
		(_port (_internal Oreg ~[7:0]reg~ 0 28 (_architecture (_out ))) (_reg ) (_simple))
		(_port (_internal go ~wire 0 28 (_architecture (_in ))) (_net  ) (_simple))
		(_type (_internal ~[3:0]wire~ 0 34 (_array ~wire ((_downto (i 3) (i 0))))))
		(_signal (_internal OPCO ~[3:0]wire~ 0 34 (_architecture (_uni ))) (_net  ))
		(_signal (_internal CP ~reg 0 44 (_architecture (_uni ))) (_reg ) (_simple))
		(_signal (_internal CLRP ~reg 0 44 (_architecture (_uni ))) (_reg ) (_simple))
		(_signal (_internal LPC_MAR ~reg 0 44 (_architecture (_uni ))) (_reg ) (_simple))
		(_signal (_internal LIR_MAR ~reg 0 44 (_architecture (_uni ))) (_reg ) (_simple))
		(_signal (_internal LPROM_ACC ~reg 0 44 (_architecture (_uni ))) (_reg ) (_simple))
		(_signal (_internal LALU_ACC ~reg 0 44 (_architecture (_uni ))) (_reg ) (_simple))
		(_signal (_internal LPROM_B ~reg 0 44 (_architecture (_uni ))) (_reg ) (_simple))
		(_signal (_internal LPROM_IR ~reg 0 44 (_architecture (_uni ))) (_reg ) (_simple))
		(_signal (_internal LIR_PC ~reg 0 44 (_architecture (_uni ))) (_reg ) (_simple))
		(_signal (_internal LACC_O ~reg 0 44 (_architecture (_uni ))) (_reg ) (_simple))
		(_type (_internal ~[2:0]reg~ 0 46 (_array ~reg ((_downto (i 2) (i 0))))))
		(_signal (_internal state ~[2:0]reg~ 0 46 (_architecture (_uni ))) (_reg ))
		(_signal (_internal next_state ~[2:0]reg~ 0 46 (_architecture (_uni ))) (_reg ) (_simple))
		(_type (_internal ~[3:0]reg~ 0 48 (_array ~reg ((_downto (i 3) (i 0))))))
		(_signal (_internal PC ~[3:0]reg~ 0 48 (_architecture (_uni ))) (_reg ))
		(_type (_internal ~[7:0]wire~ 0 49 (_array ~wire ((_downto (i 7) (i 0))))))
		(_signal (_internal WBUS ~[7:0]wire~ 0 49 (_architecture (_uni ))) (_net  ) (_simple))
		(_signal (_internal MAR ~[3:0]reg~ 0 50 (_architecture (_uni ))) (_reg ))
		(_signal (_internal PROMO ~[7:0]wire~ 0 51 (_architecture (_uni ))) (_net  ))
		(_signal (_internal IR ~[7:0]reg~ 0 52 (_architecture (_uni ))) (_reg ))
		(_signal (_internal ACC ~[7:0]reg~ 0 53 (_architecture (_uni ))) (_reg ))
		(_signal (_internal B ~[7:0]reg~ 0 54 (_architecture (_uni ))) (_reg ))
		(_signal (_internal ALUO ~[7:0]wire~ 0 55 (_architecture (_uni ))) (_net  ))
		(_signal (_internal ALUMUX ~[3:0]reg~ 0 56 (_architecture (_uni ))) (_reg ) (_simple))
		(_subprogram