📄 vz_ver4.rpt
字号:
...XX..X.X.......X...................... 5 5
NICCE XXX...X................................. 4 4
HPICE XXX...X................................. 4 4
L1/TERM_CNT2 ...XX..XXXXXXXXX.X...................... 12 12
RST_VZ ................X....................... 1 1
L1/lfsr_counter2/Q_OUT7
...XX..XXX....XX.X...................... 8 8
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
"L1/TERM_CNT1" := /"L1/TERM_CNT1" * /"L1/lfsr_counter1/Q_OUT3" *
"L1/lfsr_counter1/Q_OUT0" * "L1/lfsr_counter1/Q_OUT1" *
/"L1/lfsr_counter1/Q_OUT2" * /"L1/lfsr_counter1/Q_OUT4"
"L1/TERM_CNT1".CLKF = CLK
"L1/TERM_CNT1".RSTF = /CLK_RST
"L1/TERM_CNT1".CE = SYNC
"L1/TERM_CNT1".PRLD = GND
"L1/TERM_CNT2" := /"L1/TERM_CNT2" * "L1/lfsr_counter2/Q_OUT1" *
/"L1/lfsr_counter2/Q_OUT6" * /"L1/lfsr_counter2/Q_OUT7" *
/"L1/lfsr_counter2/Q_OUT0" * /"L1/lfsr_counter2/Q_OUT2" *
/"L1/lfsr_counter2/Q_OUT3" * /"L1/lfsr_counter2/Q_OUT4" *
/"L1/lfsr_counter2/Q_OUT5"
"L1/TERM_CNT2".CLKF = CLK
"L1/TERM_CNT2".RSTF = /CLK_RST
"L1/TERM_CNT2".CE = /SYNC
"L1/TERM_CNT2".PRLD = GND
/"L1/lfsr_counter1/Q_OUT0" := /"L1/TERM_CNT1" * /"L1/lfsr_counter1/Q_OUT1"
"L1/lfsr_counter1/Q_OUT0".CLKF = CLK
"L1/lfsr_counter1/Q_OUT0".SETF = /CLK_RST
"L1/lfsr_counter1/Q_OUT0".CE = SYNC
"L1/lfsr_counter1/Q_OUT0".PRLD = VCC
/"L1/lfsr_counter1/Q_OUT1" := /"L1/TERM_CNT1" * /"L1/lfsr_counter1/Q_OUT2"
"L1/lfsr_counter1/Q_OUT1".CLKF = CLK
"L1/lfsr_counter1/Q_OUT1".SETF = /CLK_RST
"L1/lfsr_counter1/Q_OUT1".CE = SYNC
"L1/lfsr_counter1/Q_OUT1".PRLD = VCC
/"L1/lfsr_counter1/Q_OUT2" := /"L1/TERM_CNT1" * /"L1/lfsr_counter1/Q_OUT3"
"L1/lfsr_counter1/Q_OUT2".CLKF = CLK
"L1/lfsr_counter1/Q_OUT2".SETF = /CLK_RST
"L1/lfsr_counter1/Q_OUT2".CE = SYNC
"L1/lfsr_counter1/Q_OUT2".PRLD = VCC
"L1/lfsr_counter1/Q_OUT3" := /"L1/TERM_CNT1" * "L1/lfsr_counter1/Q_OUT4"
"L1/lfsr_counter1/Q_OUT3".CLKF = CLK
"L1/lfsr_counter1/Q_OUT3".RSTF = /CLK_RST
"L1/lfsr_counter1/Q_OUT3".CE = SYNC
"L1/lfsr_counter1/Q_OUT3".PRLD = GND
/"L1/lfsr_counter1/Q_OUT4" := /"L1/TERM_CNT1" * "L1/lfsr_counter1/Q_OUT3" *
/"L1/lfsr_counter1/Q_OUT0"
+ /"L1/TERM_CNT1" * /"L1/lfsr_counter1/Q_OUT3" *
"L1/lfsr_counter1/Q_OUT0"
"L1/lfsr_counter1/Q_OUT4".CLKF = CLK
"L1/lfsr_counter1/Q_OUT4".SETF = /CLK_RST
"L1/lfsr_counter1/Q_OUT4".CE = SYNC
"L1/lfsr_counter1/Q_OUT4".PRLD = VCC
/"L1/lfsr_counter2/Q_OUT0" := /"L1/TERM_CNT2" * /"L1/lfsr_counter2/Q_OUT1"
"L1/lfsr_counter2/Q_OUT0".CLKF = CLK
"L1/lfsr_counter2/Q_OUT0".SETF = /CLK_RST
"L1/lfsr_counter2/Q_OUT0".CE = /SYNC
"L1/lfsr_counter2/Q_OUT0".PRLD = VCC
"L1/lfsr_counter2/Q_OUT1" := /"L1/TERM_CNT2" * "L1/lfsr_counter2/Q_OUT2"
"L1/lfsr_counter2/Q_OUT1".CLKF = CLK
"L1/lfsr_counter2/Q_OUT1".RSTF = /CLK_RST
"L1/lfsr_counter2/Q_OUT1".CE = /SYNC
"L1/lfsr_counter2/Q_OUT1".PRLD = GND
"L1/lfsr_counter2/Q_OUT2" := /"L1/TERM_CNT2" * "L1/lfsr_counter2/Q_OUT3"
"L1/lfsr_counter2/Q_OUT2".CLKF = CLK
"L1/lfsr_counter2/Q_OUT2".RSTF = /CLK_RST
"L1/lfsr_counter2/Q_OUT2".CE = /SYNC
"L1/lfsr_counter2/Q_OUT2".PRLD = GND
"L1/lfsr_counter2/Q_OUT3" := /"L1/TERM_CNT2" * "L1/lfsr_counter2/Q_OUT4"
"L1/lfsr_counter2/Q_OUT3".CLKF = CLK
"L1/lfsr_counter2/Q_OUT3".RSTF = /CLK_RST
"L1/lfsr_counter2/Q_OUT3".CE = /SYNC
"L1/lfsr_counter2/Q_OUT3".PRLD = GND
"L1/lfsr_counter2/Q_OUT4" := /"L1/TERM_CNT2" * "L1/lfsr_counter2/Q_OUT5"
"L1/lfsr_counter2/Q_OUT4".CLKF = CLK
"L1/lfsr_counter2/Q_OUT4".RSTF = /CLK_RST
"L1/lfsr_counter2/Q_OUT4".CE = /SYNC
"L1/lfsr_counter2/Q_OUT4".PRLD = GND
/"L1/lfsr_counter2/Q_OUT5" := /"L1/TERM_CNT2" * /"L1/lfsr_counter2/Q_OUT6"
"L1/lfsr_counter2/Q_OUT5".CLKF = CLK
"L1/lfsr_counter2/Q_OUT5".SETF = /CLK_RST
"L1/lfsr_counter2/Q_OUT5".CE = /SYNC
"L1/lfsr_counter2/Q_OUT5".PRLD = VCC
/"L1/lfsr_counter2/Q_OUT6" := /"L1/TERM_CNT2" * /"L1/lfsr_counter2/Q_OUT7"
"L1/lfsr_counter2/Q_OUT6".CLKF = CLK
"L1/lfsr_counter2/Q_OUT6".SETF = /CLK_RST
"L1/lfsr_counter2/Q_OUT6".CE = /SYNC
"L1/lfsr_counter2/Q_OUT6".PRLD = VCC
"L1/lfsr_counter2/Q_OUT7".T = "L1/TERM_CNT2" * /"L1/lfsr_counter2/Q_OUT7"
+ /"L1/TERM_CNT2" * /"L1/lfsr_counter2/Q_OUT1" *
"L1/lfsr_counter2/Q_OUT6" * "L1/lfsr_counter2/Q_OUT0"
;Imported pterms FB2_12
+ /"L1/TERM_CNT2" * "L1/lfsr_counter2/Q_OUT1" *
"L1/lfsr_counter2/Q_OUT6" * /"L1/lfsr_counter2/Q_OUT0"
+ /"L1/TERM_CNT2" * "L1/lfsr_counter2/Q_OUT1" *
/"L1/lfsr_counter2/Q_OUT6" * "L1/lfsr_counter2/Q_OUT0"
;Imported pterms FB2_14
+ /"L1/TERM_CNT2" * /"L1/lfsr_counter2/Q_OUT1" *
/"L1/lfsr_counter2/Q_OUT6" * /"L1/lfsr_counter2/Q_OUT0"
"L1/lfsr_counter2/Q_OUT7".CLKF = CLK
"L1/lfsr_counter2/Q_OUT7".SETF = /CLK_RST
"L1/lfsr_counter2/Q_OUT7".CE = /SYNC
"L1/lfsr_counter2/Q_OUT7".PRLD = VCC
DON = /DISPLAY
RST_VZ = RSTIN
/HPICE = /A22 * A21 * A20 * /EXTCE
SYNC.T = "L1/TERM_CNT2" * /"L1/TERM_CNT1"
+ /"L1/TERM_CNT2" * "L1/TERM_CNT1"
SYNC.CLKF = CLK
SYNC.RSTF = /CLK_RST
SYNC.PRLD = GND
/NICCE = /A22 * /A21 * /A20 * /EXTCE
**************************** Device Pin Out ****************************
Device : XC9536XL-10-VQ44
R
N H S R
I P T S
T T T C I T _ V G T T
I I I C C I V C N D I
E E E E E E Z C D O N
--------------------------------
/33 32 31 30 29 28 27 26 25 24 23 \
TIE | 34 22 | TIE
VCC | 35 21 | TIE
TIE | 36 20 | TIE
DON | 37 19 | TIE
DISPLAY | 38 XC9536XL-10-VQ44 18 | SYNC
TIE | 39 17 | GND
TIE | 40 16 | CLK
TIE | 41 15 | VCC
TIE | 42 14 | CLK_RST
A20 | 43 13 | TIE
A21 | 44 12 | TIE
\ 1 2 3 4 5 6 7 8 9 10 11 /
--------------------------------
A E T G T T T T T T T
2 X I N I I I I D M C
2 T E D E E E E I S K
C
E
Legend : NC = Not Connected, unbonded pin
TIE = Tie pin to GND or board trace driven to valid logic level
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : XC9536XL-10-VQ44
Use Timing Constraints : ON
Ignore Assignments In Design File : OFF
Create Programmable Ground Pins : OFF
Use Advanced Fitting : ON
Use Local Feedback : OFF
Use Pin Feedback : OFF
Default Power Setting : STD
Default Output Slew Rate : FAST
Guide File Used : NONE
Multi Level Logic Optimization : ON
Timing Optimization : ON
Power/Slew Optimization : OFF
High Fitting Effort : ON
Automatic Wire-ANDing : OFF
Xor Synthesis : ON
D/T Synthesis : ON
Use Boolean Minimization : ON
Global Clock(GCK) Optimization : ON
Global Set/Reset(GSR) Optimization : ON
Global Output Enable(GTS) Optimization : ON
Collapsing pterm limit : 25
Collapsing input limit : 54
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