pll.v

用VHDL写的数字锁相环程序 pll.vhd为源文件 pllTB.vhd为testbench

      intPllActive2 <= intPllActive1;
      pllActive <= intPllActive2;
      end

//latch and triple bank pllActive to generate clkResetL   

always @(posedge vcoClk or negedge iResetL)
   if(!iResetL)
      begin
      intClkResetL1 <= 1'b0;
      intClkResetL2 <= 1'b0;
      iClkResetL <= 1'b0;
      end 
   else
      begin
      intClkResetL1 <=  iPllLock | intClkResetL1;
      intClkResetL2 <= intClkResetL1;
      iClkResetL <= intClkResetL2;
      end

//generate IPDReset  

always @(posedge refClk or negedge iResetL)
   if(!iResetL)
      begin
      intIPDReset <= 1'b0;
      IPDReset <= 1'b0;
      end
   else 
      begin
      intIPDReset <= 1'b1;
      IPDReset <= intIPDReset;
      end

assign iResetL = porL && sleepL;

assign pllLock = iResetL && iPllLock;
assign sysResetL = iResetL && iSysResetL;
assign clkResetL = iResetL && iClkResetL;


endmodule

/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
///
/// Module      : pllCore
/// Author      : Parthus Technologies PLC
///_______________________________________________________________________
///
///        Copyright (c) 2002 Parthus Technologies PLC.
///
/// This code is confidential and proprietary product of Parthus. Any
/// unauthorized use, reproduction or transfer of this code is strictly
/// prohibited.
///_______________________________________________________________________
///
/// Description: This file contains a behavioural model of the analog  
/// 	         pll core.
///		 
///_______________________________________________________________________
///
///
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////

//`define SETTLINGTIME4215 237000
`define SETTLINGTIME4215 23000

`define DIVCLKNOM4215 4.500000e-3
`define VCOCLKNOM4215 288.000000e-3

`define DIVCLKTOL4215 0.300000
`define VCOCLKTOL4215 0.250000

`define KVCOTYP4215 966.571429

`define CLKTOL 0.01
`define Vt 0.5


module pllCore4215 ( divClkin, porL, sleepL, VCODelayed,
	     FBD,
	     fbClk, lockDetAsync, vcoClk, filterVoltageBus);

input divClkin;        
input porL; 
input sleepL;
input VCODelayed;
input [7:0] FBD;

output fbClk;
output lockDetAsync;    
output vcoClk;
output [63:0] filterVoltageBus;

reg iFbClk, vcoClk, lockDetAsync; 
wire divClk,fbClk;

reg divClkPeriodChanged, FBDChanged;
reg noDivClk, invalidDivClk, invalidVcoClk, resetDone;
reg startTimeSet, settlingTimeComplete;
reg [8:0] countFBD;		//1 more bit to allow for a count to 256
reg [7:0] FBDPrev; 

reg invert,done;

reg divClkReset,intDivClkReset1,intDivClkReset2;
reg vcoValid,intVcoValid1,intVcoValid2;
wire invalidInput, iResetL, resetDoneDelayed;

real divClkRe1, divClkRe2, divClkPeriod, divClkPeriodPrev;
real vcoClkHalfPeriod;
real vcoClkRe,VCODelayedRe,tdbuf;
real lockStartTime;
real filterVoltage;
real starttime,currtime,reqtime,delta;

integer i;

wire [63:0] filterVoltageBus = $realtobits(filterVoltage);

assign divClk = divClkin;


initial 
   begin
   divClkPeriodChanged = 0;
   divClkPeriod = 1/`DIVCLKNOM4215;          
   divClkPeriodPrev = 0;
   FBDChanged = 0;
   resetDone = 0;
   divClkReset = 0;
   intDivClkReset1 = 0;
   intDivClkReset2 = 0;
   divClkRe1 = 0;
   divClkRe2 = 0;
   vcoClkHalfPeriod = 0;
   vcoClkRe = 0;
   VCODelayedRe = 0;
   tdbuf = 0;
   noDivClk = 0;
   invalidDivClk = 0;
   invalidVcoClk = 0;
   settlingTimeComplete = 0;
   lockStartTime = 0;
   startTimeSet = 0;
   vcoClk = 0;
   lockDetAsync = 0;
   invert = 0;
   vcoValid = 0;
   intVcoValid1 = 0;
   intVcoValid2 = 0;
   done = 0;
   starttime = 0;
   currtime = 0;
   reqtime = 0;
   delta = 0;
   end


// and porL and sleepL

assign iResetL = porL & sleepL;

//Wait until there have been several divClk cycles after reset before monitoring for invalid input

always @(posedge divClk or negedge iResetL)
   if(!iResetL)
      begin
      intDivClkReset1 <= 1'b0;
      intDivClkReset2 <= 1'b0;
      divClkReset <= 1'b0;
      end
   else
      begin
      intDivClkReset1 <= 1'b1;
      intDivClkReset2 <= intDivClkReset1;
      divClkReset <= intDivClkReset2;
      end

//Wait until there have been several vcoClk cycles to issue a valid signal

always @(posedge vcoClk or negedge iResetL)
   if(!iResetL)
      begin
      intVcoValid1 <= 1'b0;
      intVcoValid2 <= 1'b0;
      vcoValid <= 1'b0;
      end
   else
      begin
      intVcoValid1 <= 1'b1;
      intVcoValid2 <= intVcoValid1;
      vcoValid <= intVcoValid2;
      end



//Calculate the input clock period, monitor changes in it and make sure that its within range

always @ (posedge divClkin) 
   begin
   divClkRe1 = divClkRe2;
   divClkRe2 = $realtime;

   divClkPeriodPrev = divClkPeriod;
   divClkPeriod = divClkRe2 - divClkRe1;

   if(((divClkPeriod - divClkPeriodPrev) > `CLKTOL) || ((divClkPeriodPrev - divClkPeriod) > `CLKTOL) )
      divClkPeriodChanged = 1;
   else
      divClkPeriodChanged = 0;

   if(divClkReset)
      if( ((1/divClkPeriod) < (`DIVCLKNOM4215-(`DIVCLKNOM4215*`DIVCLKTOL4215))) || ((1/divClkPeriod) > (`DIVCLKNOM4215+(`DIVCLKNOM4215*`DIVCLKTOL4215))) )
         invalidDivClk = 1;
      else
         invalidDivClk = 0;
   else
      invalidDivClk = 0;

   end

//because if there are no divClk edges then invalidDivClk cannot become active as it posedge divClk triggered

always
   #(1/(2.0*`DIVCLKNOM4215)) noDivClk = (($realtime - divClkRe2)> (2.0/(`DIVCLKNOM4215-(`DIVCLKNOM4215*`DIVCLKTOL4215)))) ? 1 : 0;

//Monitor for changes in the feedback divider number

always @ (posedge divClk) 
   begin 
   if(FBDPrev != FBD)
      FBDChanged = 1;
   else
      FBDChanged = 0;
   FBDPrev = FBD;
   end

//Calculate the vco clock period, monitor changes in it and make sure that its within range

always @ (posedge divClkin) 
   begin 
   vcoClkHalfPeriod = divClkPeriod/((FBD+1)*2.0);

   if(vcoValid)
      begin
      if( ((1/(vcoClkHalfPeriod*2.0)) < (`VCOCLKNOM4215-(`VCOCLKNOM4215*`VCOCLKTOL4215))) || ((1/(vcoClkHalfPeriod*2.0)) > (`VCOCLKNOM4215+(`VCOCLKNOM4215*`VCOCLKTOL4215))) )
         invalidVcoClk = 1;
      else
         invalidVcoClk = 0;
      end
   else
      invalidVcoClk = 0;

   end

//Measure buffer delay

always @ (posedge vcoClk) 
   begin 
   if(!vcoValid)
      begin
      tdbuf = 0;
      done = 0;
      end
   else if (done)
      tdbuf = tdbuf; 
   else
      begin
      vcoClkRe = $realtime;
      @(posedge VCODelayed) VCODelayedRe = $realtime;

      if((VCODelayedRe-vcoClkRe)>(vcoClkHalfPeriod*2.0))
         begin
         tdbuf = VCODelayedRe-vcoClkRe-(vcoClkHalfPeriod*2.0);
         invert = 0;
         end
      else if((VCODelayedRe-vcoClkRe)>vcoClkHalfPeriod)
         begin
         tdbuf = (vcoClkHalfPeriod*2.0)-(VCODelayedRe-vcoClkRe);
         invert = 0;
         end
      else
         begin
         tdbuf = VCODelayedRe-vcoClkRe;
         tdbuf = (divClkPeriod/2.0)-tdbuf;
         invert = 1;
         end
      done = 1;
      end
   end

//Check that always get an initial porL and also after going to an invalid input or vco clock frequency and back

//15/01/02 - added FBDChanged,divClkPeriodChanged to invalidInput to force a porl after changing divider ratio's

assign invalidInput = divClkReset ? (invalidDivClk || invalidVcoClk || noDivClk || FBDChanged || divClkPeriodChanged) : 0;

always @(porL or posedge invalidInput)
   begin 
   if(invalidInput)
      resetDone = 0;
   else if(porL && (!invalidInput))
      resetDone = 1;
   else if(!porL) 
      resetDone = 0;
   else
      resetDone = resetDone;
   end

assign #(6.0*vcoClkHalfPeriod) resetDoneDelayed = resetDone;

//Generate lock detect signal

always @ (posedge divClk or sleepL or invalidInput or resetDone or FBDChanged or divClkPeriodChanged)
   begin
   if(!(resetDone && sleepL) || invalidInput || FBDChanged || divClkPeriodChanged)
      begin
      lockDetAsync = 0;
      settlingTimeComplete = 0;
      startTimeSet = 0;
      end
   else
      begin
      if(!startTimeSet)
         begin
         lockStartTime = $realtime;
         startTimeSet = 1;
         end

      if(($realtime - lockStartTime) > `SETTLINGTIME4215)
         settlingTimeComplete = 1;

      if(settlingTimeComplete) 
         lockDetAsync = 1; 
      end     
   end


//Generate Vco Clock

always
   begin
   if(!sleepL)
      #1 vcoClk = 0;
   else if((!divClkReset) || (!resetDoneDelayed))   //add memory so that there can be an extra couple of vcoClk cycles to
      #1 vcoClk = 1'bx;				    //clear the pllLock in the digital
   else
      begin 
      @(posedge divClk) vcoClk = 1;
      starttime = $realtime;
      i=1;
      #vcoClkHalfPeriod vcoClk = 0;     
      repeat(FBD) begin
         #vcoClkHalfPeriod vcoClk = 1;
         currtime = $realtime-starttime;
         reqtime = 2.0*vcoClkHalfPeriod*i;
         delta=reqtime-currtime;
         i=i+1;
         if((vcoClkHalfPeriod+delta) < 0)
             #(vcoClkHalfPeriod) vcoClk = 0;
         else
             #(vcoClkHalfPeriod+delta) vcoClk = 0;
         end
      end
   end


//Generate Feedback Clock

always @(posedge VCODelayed or sleepL or resetDone)
   begin
   if((!divClkReset) || (!resetDone))
      begin
      iFbClk = 1'bx;
      countFBD = 0;
      end
   else if(!sleepL)
      begin
      iFbClk = 0;
      countFBD = 0;
      end
   else
      begin 
      if(countFBD == (FBD+1))
         begin 
         iFbClk = 1;
         countFBD = 0;
         end
      else
         iFbClk = 0;
      countFBD = countFBD + 1;
      end
   end

assign fbClk = (FBD == 0) ? VCODelayed : iFbClk;

//Generate Filter Voltage

always @(vcoClk)
   begin
   if((!resetDone) || (!sleepL))
      filterVoltage = 0;     //reals cannot be x
   else
      filterVoltage = (1/(`KVCOTYP4215*vcoClkHalfPeriod*2.0*1e-3))+`Vt;   
   end

endmodule