pll.vhd

用VHDL写的数字锁相环程序 pll.vhd为源文件 pllTB.vhd为testbench

--///////////////////////////////////////////////////////////////////////////
--///////////////////////////////////////////////////////////////////////////
--/
--/ File        : pll.vhd
--/ Author	: ParthusCeva Inc.
--// Date	: Mon Feb 17 06:08:33 2003
--// Info	: Job No = 12364215
--/_______________________________________________________________________
--/ 
--/        Copyright (c)  ParthusCeva Inc.
--/ 
--/ This code is confidential and proprietary product of ParthusCeva. Any
--/ unauthorized use, reproduction or transfer of this code is strictly
--/ prohibited.
--/_______________________________________________________________________
--/ 
--/		 
--/_______________________________________________________________________
--/ 
--/
--///////////////////////////////////////////////////////////////////////////
--///////////////////////////////////////////////////////////////////////////

--///////////////////////////////////////////////////////////////////////////
--///////////////////////////////////////////////////////////////////////////
--/
--/ Entity & Architecture      : xtop4215
--/ Author			: ParthusCeva Inc.
--/_______________________________________________________________________
--/ 
--/        Copyright (c)  ParthusCeva Inc.
--/ 
--/ This code is confidential and proprietary product of ParthusCeva. Any
--/ unauthorized use, reproduction or transfer of this code is strictly
--/ prohibited.
--/_______________________________________________________________________
--/ 
--/ Description: This entity/architecture contains a VHDL behavioural  
--/ 	         (non-synthesizable) model of the entire PLL.		 
--/_______________________________________________________________________
--/ 
--/
--///////////////////////////////////////////////////////////////////////////
--///////////////////////////////////////////////////////////////////////////


library ieee;
use ieee.std_logic_1164.all;

entity xtop4215 is
	port (
		refClk		: in  std_logic;
		porL		: in  std_logic;
		sleepL		: in  std_logic;
		forceBypass	: in  std_logic;
		FBD0		: in  std_logic;
		FBD1		: in  std_logic;
		FBD2		: in  std_logic;
		FBD3		: in  std_logic;
		FBD4		: in  std_logic;
		FBD5		: in  std_logic;
		FBD6		: in  std_logic;
		FBD7		: in  std_logic;
		IPD0		: in  std_logic;
		IPD1		: in  std_logic;
		IPD2		: in  std_logic;
		IPD3		: in  std_logic;
		IPD4		: in  std_logic;
		IPD5		: in  std_logic;
		IPD6		: in  std_logic;
		IPD7		: in  std_logic;
		xClk01		: out std_logic;
		xClk02		: out std_logic;
		xClk03		: out std_logic;
		pllLock		: out std_logic;
		sysResetL	: out std_logic);

end xtop4215;

architecture beh of xtop4215 is

component pllCore4215
	port (
		divClkin	: in  std_logic;
		porL		: in  std_logic;
		sleepL		: in  std_logic;
		VCODelayed	: in  std_logic;
		FBD		: in  std_logic_vector(7 downto 0);
		fbClk		: out std_logic;
		lockDetAsync	: out std_logic;
		vcoClk		: buffer std_logic;
		filterVoltageBus: out real);
end component;

component pllDig4215
	port (
		porL		: in  std_logic;
		sleepL		: in  std_logic;
		lockDetAsync	: in  std_logic;
		refClk		: in  std_logic;
		vcoClk		: in  std_logic;
		forceBypass	: in  std_logic;
		divClk		: buffer std_logic;
		IPD		: in  std_logic_vector(7 downto 0);
		xClk01		: out  std_logic;
		xClk02		: out  std_logic;
		xClk03		: out  std_logic;
		pllLock		: out std_logic;
		sysResetL	: out std_logic);
end component;

signal divClk : std_logic;
signal fbClk : std_logic;
signal iFBD : std_logic_vector(7 downto 0);
signal iIPD : std_logic_vector(7 downto 0);
signal vcoClk : std_logic;
signal lockDetAsync : std_logic;
signal filterVoltageBus : real;

begin  -- beh

-- synopsys translate_off

	iFBD <= FBD7 & FBD6 & FBD5 & FBD4 & FBD3 & FBD2 & FBD1 & FBD0;
	iIPD <= IPD7 & IPD6 & IPD5 & IPD4 & IPD3 & IPD2 & IPD1 & IPD0;

IpllCore : pllCore4215 
	port map (
		divClkin	=> divClk,
		porL		=> porL,
		sleepL		=> sleepL,
		FBD => iFBD,
		VCODelayed	=> vcoClk,
		fbClk		=> fbClk,
		lockDetAsync	=> lockDetAsync,
		vcoClk		=> vcoClk,
		filterVoltageBus=> filterVoltageBus);

IpllDig : pllDig4215 
	port map (
		porL		=> porL,
		sleepL		=> sleepL,
		lockDetAsync	=> lockDetAsync,
		refClk		=> refClk,
		vcoClk		=> vcoClk,
		forceBypass	=> forceBypass,
		divClk		=> divClk,
		IPD => iIPD,
		xClk01	=> xClk01,
		xClk02	=> xClk02,
		xClk03	=> xClk03,
		pllLock		=> pllLock,
		sysResetL	=> sysResetL);

-- synopsys translate_on

end beh;

--///////////////////////////////////////////////////////////////////////////
--///////////////////////////////////////////////////////////////////////////
--/
--/ entity & architecture       : pllDig
--/ Author			: ParthusCeva Inc.
--/_______________________________________________________________________
--/ 
--/        Copyright (c)  ParthusCeva Inc.
--/ 
--/ This code is confidential and proprietary product of ParthusCeva. Any
--/ unauthorized use, reproduction or transfer of this code is strictly
--/ prohibited.
--/_______________________________________________________________________
--/ 
--/ Description: This entity & architecture contains a VHDL behavioural  
--/ 	         (non-synthesizable) model of the PLL digital logic.
--/		 
--/_______________________________________________________________________
--/ 
--/
--///////////////////////////////////////////////////////////////////////////
--///////////////////////////////////////////////////////////////////////////


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

entity pllDig4215 is

	port (
		porL		: in  std_logic;
		sleepL		: in  std_logic;
		lockDetAsync	: in  std_logic;
		refClk		: in  std_logic;
		vcoClk		: in  std_logic;
		forceBypass	: in  std_logic;
		divClk		: buffer std_logic;
		IPD		: in  std_logic_vector(7 downto 0);
		xClk01		: out std_logic;
		xClk02		: out std_logic;
		xClk03		: out std_logic;
		pllLock		: out std_logic;
		sysResetL	: out std_logic);

end pllDig4215;

architecture beh of pllDig4215 is

component resetBlock4215
	port (
		porL		: in  std_logic;       -- Power on Reset
		sleepL		: in  std_logic;
		lockDetAsync	: in  std_logic;       --  Lock Detect Asynchronous Signal
		vcoClk		: in  std_logic;
		slowestClk	: in  std_logic;
		refClk		: in  std_logic;
		pllLock		: out std_logic;
		sysResetL	: out std_logic;
		IPDReset	: out std_logic;
		clkResetL	: out std_logic
);
end component;

signal init1		: std_logic := '1';
signal start1		: integer := 6;
signal hi1		: integer := 4;
signal lo1		: integer := 6;

signal init2		: std_logic := '1';
signal start2		: integer := 6;
signal hi2		: integer := 6;
signal lo2		: integer := 6;

signal init3		: std_logic := '1';
signal start3		: integer := 10;
signal hi3		: integer := 8;
signal lo3		: integer := 10;


signal IPDReset       : std_logic;
signal clkResetL      : std_logic;
signal intSleepL      : std_logic;
signal intLockDetAsync : std_logic;
signal clkin          : std_logic;

signal iDivClk	:std_logic := '0';
signal i_xClk01		: std_logic;
signal i_xClk02		: std_logic;
signal i_xClk03		: std_logic;

begin  -- beh

-- synopsys translate_off

iResetBlock : resetBlock4215
	port map (
		porL		=> porL,
		sleepL		=> intSleepL,
		lockDetAsync	=> intLockDetAsync,
		vcoClk		=> clkin,
		slowestClk => i_xClk03,
		refClk		=> refClk,
		pllLock		=> pllLock,
		sysResetL	=> sysResetL,
		IPDReset	=> IPDReset,
		clkResetL	=> clkResetL);

	intSleepL 	<= '1' when forceBypass = '1' else sleepL;
	intLockDetAsync <= '1' when forceBypass = '1' else lockDetAsync;
	clkin 		<= refClk when forceBypass = '1' else vcoClk;

	process 
		begin  -- process
		wait until IPDReset'event and IPDReset = '1';
		wait until (refClk'event and refClk = '1') or IPDReset'event;

		while IPDReset = '1' loop
			iDivClk <= not iDivClk;

			for I in 1 to CONV_INTEGER(UNSIGNED(IPD)) + 1 loop
				wait until refClk'event or IPDReset'event;        
			end loop;  -- I

			iDivClk <= not iDivClk;

			if IPDReset = '1' then
				for I in 1 to CONV_INTEGER(UNSIGNED(IPD)) + 1 loop
					wait until refClk'event or IPDReset'event;        
				end loop;  -- I
			end if;
		end loop;
		end process;


	process(refClk,iDivClk)
		begin
		case IPD is
			when "00000000" => divClk <= refClk;
			when others => divClk <= iDivClk;
		end case;
	end process;

	process
		begin  -- process
		i_xClk01 <= init1;

		loop
			wait until clkResetL'event and clkResetL = '1';

			i_xClk01 <= init1;

			for I in 1 to start1 loop
				wait on clkin, clkResetL;
			end loop;

			while clkResetL = '1' loop
				i_xClk01 <= not i_xClk01;

				for I in 1 to hi1 loop
					wait on clkin, clkResetL;
				end loop;

				i_xClk01 <= not i_xClk01;

				if clkResetL = '1' then
					for I in 1 to lo1 loop
						wait on clkin, clkResetL;
					end loop;  -- I
				end if;
			end loop;
		end loop;
	end process;

	xClk01 <= i_xClk01;

	process
		begin  -- process
		i_xClk02 <= init2;

		loop
			wait until clkResetL'event and clkResetL = '1';

			i_xClk02 <= init2;

			for I in 1 to start2 loop
				wait on clkin, clkResetL;
			end loop;

			while clkResetL = '1' loop
				i_xClk02 <= not i_xClk02;

				for I in 1 to hi2 loop
					wait on clkin, clkResetL;
				end loop;

				i_xClk02 <= not i_xClk02;

				if clkResetL = '1' then
					for I in 1 to lo2 loop
						wait on clkin, clkResetL;
					end loop;  -- I
				end if;
			end loop;
		end loop;
	end process;

	xClk02 <= i_xClk02;

	process
		begin  -- process
		i_xClk03 <= init3;

		loop
			wait until clkResetL'event and clkResetL = '1';

			i_xClk03 <= init3;

			for I in 1 to start3 loop
				wait on clkin, clkResetL;
			end loop;

			while clkResetL = '1' loop
				i_xClk03 <= not i_xClk03;

				for I in 1 to hi3 loop
					wait on clkin, clkResetL;
				end loop;

				i_xClk03 <= not i_xClk03;

				if clkResetL = '1' then
					for I in 1 to lo3 loop
						wait on clkin, clkResetL;
					end loop;  -- I
				end if;
			end loop;
		end loop;
	end process;

	xClk03 <= i_xClk03;


-- synopsys translate_on

end beh;

library ieee;
use ieee.std_logic_1164.all;

entity resetBlock4215 is

	port (
		porL		: in  std_logic;       -- Power on Reset
		sleepL		: in  std_logic;
		lockDetAsync	: in  std_logic;       --  Lock Detect Asynchronous Signal
		vcoClk		: in  std_logic;
		slowestClk	: in  std_logic;
		refClk		: in  std_logic;
		pllLock		: out std_logic;
		sysResetL	: out std_logic;
		IPDReset	: out std_logic;
		clkResetL	: out std_logic);

end resetBlock4215;

architecture beh of resetBlock4215 is

-- synopsys translate_off

signal pllActive 	: std_logic := '0';
signal intIPDReset 	: std_logic := '0';
signal intPllActive1 	: std_logic := '0';
signal intPllActive2 	: std_logic := '0';
signal iClkResetL 	: std_logic := '0';
signal intClkResetL1 	: std_logic := '0';
signal intClkResetL2 	: std_logic := '0';
signal iPllLock 	: std_logic := '0';
signal intPllLock1 	: std_logic := '0';
signal intPllLock2 	: std_logic := '0';
signal iSysResetL 	: std_logic := '0';
signal intSysResetL1 	: std_logic := '0';
signal intSysResetL2 	: std_logic := '0';
signal iResetL 	: std_logic := '0';

begin  -- beh

	-- purpose: Tripple Bank lockDetASync
	-- type   : sequential
	-- inputs : vcoClk, iResetL, lockDetASync
	-- outputs: iPllLock
	process (vcoClk, iResetL)
		begin  -- process
		if iResetL = '0' then               -- asynchronous reset (active low)
			intPllLock1 	<= '0';
			intPllLock2 	<= '0';
			iPllLock 		<= '0';
		elsif vcoClk'event and vcoClk = '1' then  -- rising clock edge
			intPllLock1 	<= lockDetAsync;
			intPllLock2 	<= intPllLock1;
			iPllLock 		<= intPllLock2;
		end if;
	end process;

	-- purpose: latch pllLock to form SysResetL 3 slowestClk cycles after pllLock
	-- type   : sequential
	-- inputs : slowestClk, iResetL, iPllLock
	-- outputs: iSysResetL
	process (slowestClk, iResetL)
		begin  -- process
		if iResetL = '0' then               -- asynchronous reset (active low)
			intSysResetL1 	<= '0';
			intSysResetL2 	<= '0';
			iSysResetL 	<= '0';
		elsif slowestClk'event and slowestClk = '1' then  -- rising clock edge
			intSysResetL1 	<= iPllLock;
			intSysResetL2 	<= intSysResetL1;
			iSysResetL 	<= iSysResetL or intSysResetL2;
		end if;
	end process;

	-- purpose: generate pllActive
	-- type   : sequential