convl3_en.v

来自「发一个基于ModelSim仿真的Verilog源代码包」· Verilog 代码 · 共 26 行

/******************************************************/
/* module convl3_en                              */
/******************************************************/

/* This is the encoder. 
X2N (msb) X1N form the 2-bit input message, X2NX1N. 
Y2N(msb), Y1N, and Y0N form the 3-bit encoded signal, YN (for a total constellation of 8
PSK signals that will be transmitted). The encoder uses a state
machine with four states to generate the 4-bit output, YN, from the
2-bit input, X2NX1n.Polynomial:   K=3
*/
module convl3_en(X2N,X1N,Y2N,Y1N,Y0N,clk,res);
input  X2N,X1N,clk,res; 
output Y2N,Y1N,Y0N;
wire   X1N_1,X1N_2,Y2N,Y1N,Y0N;

//X1N ,X2N is direct input data,x1N_0 is sampled valid data from X1N at clock edage 
dff dff_1(X1N,X1N_1,clk,res); 
dff dff_2(X1N_1,X1N_2,clk,res);

assign Y2N=X2N; 
assign Y1N=X1N ^ X1N_2; 
assign Y0N=X1N_1; 
endmodule