convlen3_test.v

发一个基于ModelSim仿真的Verilog源代码包

/*****************************************************/
/* module convlen3_test                         */
/*****************************************************/
//
//

/* This is the top-level module, convlen_test, to test the convolutional coder. 
The 2-bit message, X, is convolutionally encoded to a 3-bit signal, Y.
In this module the message X is generated using accurate delay.
The digital 3-bit signal Y is coded out. */
//

//

`timescale 1ns/1ns 

module convlen3_test;

wire [2:0] Y; // encoder output vector Y[2:0]
reg  [1:0] X;       // encoder input  vector X[1:0]
reg Clk, Res; // system clock and control input : clock and reset

//always #500 $display("t    Clk X Y ");

//initial $monitor("%4g",$time,,Clk,,,,X,,Y);

//initial $dumpvars;

/* initial #3000 $finish;

always #10 Clk = ~Clk; // to generate clock from t=0, and T=20 units 

initial 	   // 注意！！！－使用non-block赋值和内嵌式时延，可以产生精确的绝对时延 .

    
	begin 	  // 产生测试输入序列 X,注意X的变化应当和Clk的有效边沿对齐
	    X[1] <= 0; 
	    X[0] <= 0;   

	    Clk <= 0;
	    Res <=#2 1;
		Res <=#5 0;
		 
		X[1] <= #9 1; 
	    X[0] <= #9 1;

		X[1]<= #29 0;
		X[0]<= #29 0;

		X[1]<= #69 1;
		X[0]<= #69 1;

		X[1]<= #89 0;
		X[0]<= #89 0;

		X[1]<= #109 1;
		X[0]<= #109 1;

		X[1]<= #129 0;
		X[0]<= #129 0;
	end 
// Hit reset after inputs are stable.

//下面是卷积编码器示例化			*/


initial #3000 $finish;
always #50 Clk = ~Clk; 
initial 
	begin 
		Clk = 0;
		X = 3; // No special reason to start at 3.
		#60 Res = 1;
		#10 Res = 0; 
	end // Hit reset after inputs are stable.

always @(posedge Clk) #1 X = X + 1; // Drive the input with a counter.

convl3_en v_1(X[1],X[0],Y[2],Y[1],Y[0],Clk,Res);

endmodule