_primary.vhd

来自「发一个基于ModelSim仿真的Verilog源代码包」· VHDL 代码 · 共 14 行

library verilog;
use verilog.vl_types.all;
entity convl3_en is
    port(
        x2n             : in     vl_logic;
        x1n             : in     vl_logic;
        y2n             : out    vl_logic;
        y1n             : out    vl_logic;
        y0n             : out    vl_logic;
        clk             : in     vl_logic;
        res             : in     vl_logic
    );
end convl3_en;