_primary.vhd

来自「发一个基于ModelSim仿真的Verilog源代码包」· VHDL 代码 · 共 14 行

library verilog;
use verilog.vl_types.all;
entity dff is
    generic(
        cardinality     : integer := 1
    );
    port(
        d               : in     vl_logic_vector;
        q               : out    vl_logic_vector;
        clock           : in     vl_logic;
        reset           : in     vl_logic
    );
end dff;