keyscan.v

发一个基于ModelSim仿真的Verilog源代码包

//
`timescale 1ms/100us
module keyscan(rst,oe,rd,cs,scanclk,y,r,dout,int);
//inputs
input rst,oe,rd,cs,scanclk;//reset,output enable,read (from uP),
                           //chip select, scan keyboard clock
input[3:0] y;  //colums inputs, the entered key lattice dot
//outputs
output[3:0] dout,r; //out data  to uP ,scan out
output int;			 // out to uP to apply interrupt to read 
//outputs register and temp variable reg
reg [3:0] dout,r;
reg [3:0] pres_state,next_state;
reg int,hold;//hold  is temp node signal

//statemachine register
parameter sr=4'b1111,s0=4'b1110,s1=4'b1101,s2=4'b1011,s3=4'b0111;//,srst=4'b0000;

//rst->asych reset ,state transition machine 
always @(posedge scanclk or posedge rst) 	  //when @edge ,then endowed value at the edge point,
	begin:statereg
		if(rst) pres_state<=sr;
			
	    else   	pres_state<=next_state;
	end
//as above state machine
always @ (pres_state or hold) 
		begin:fsm          
	   	case(pres_state)
			sr:	next_state=s0;
			s0:					
				case (!hold)
					1'b1: next_state=s1;
		        	1'b0: next_state=pres_state;
				endcase
			s1:	
			    case (!hold)
					1'b1: next_state=s2;
		        	1'b0: next_state=pres_state;
				endcase
			s2:	
				case (!hold)
					1'b1: next_state=s3;
		        	1'b0: next_state=pres_state;
				endcase	    
			s3:	
				case (!hold)
					1'b1: next_state=s0;
		        	1'b0: next_state=pres_state;
				endcase
		   	default: next_state=s0;            
	 	endcase
	  end

//Mealy FSM outputs,combin outputs
always @ (cs or rd or y or pres_state)
		begin:output_data 
		r=pres_state;                
		hold =!(y[0]&y[1]&y[2]&y[3]);
		int =!hold |(y[0]&y[1]&y[2]&y[3]);
		
	case(cs)
	   1'b1:
	   begin
	   	case(pres_state)
		   	
			s0:case (y)
				4'b1110:dout=4'b0000;
				4'b1101:dout=4'b0001;
				4'b1011:dout=4'b0010;
				4'b0111:dout=4'b0011;
				endcase
									
			s1:	case (y)
				4'b1110:dout=4'b0100;
				4'b1101:dout=4'b0101;
				4'b1011:dout=4'b0110;
				4'b0111:dout=4'b0111;
				endcase

			s2:	case (y)
				4'b1110:dout=4'b1000;
				4'b1101:dout=4'b1001;
				4'b1011:dout=4'b1010;
				4'b0111:dout=4'b1011;
				endcase
	
			s3:	case (y)
				4'b1110:dout=4'b1100;
				4'b1101:dout=4'b1101;
				4'b1011:dout=4'b1110;
				4'b0111:dout=4'b1111;
				endcase
			default:dout=4'bzzzz;
		endcase
	   end
	  1'b0:dout=4'bzzzz;
	  endcase 
	end	

endmodule