_primary.vhd

来自「发一个基于ModelSim仿真的Verilog源代码包」· VHDL 代码 · 共 23 行

library verilog;
use verilog.vl_types.all;
entity keyscan is
    generic(
        sr              : integer := 15;
        s0              : integer := 14;
        s1              : integer := 13;
        s2              : integer := 11;
        s3              : integer := 7
    );
    port(
        rst             : in     vl_logic;
        oe              : in     vl_logic;
        rd              : in     vl_logic;
        cs              : in     vl_logic;
        scanclk         : in     vl_logic;
        y               : in     vl_logic_vector(3 downto 0);
        r               : out    vl_logic_vector(3 downto 0);
        dout            : out    vl_logic_vector(3 downto 0);
        int             : out    vl_logic
    );
end keyscan;