keyscan_test.v

发一个基于ModelSim仿真的Verilog源代码包

`timescale 1ms/100us 
module keyscan_test;

reg  [3:0] COL;       // keyboard  input  columns
reg CLK,RST,RD,OE,CS;//scan_clock, asynch_reset,read <-uP,out_enable,chip_select

wire [3:0] DOUT,R; // data output to uP ,scan data
wire INT;		// output to uP to interrupt to read encoded key data


initial #30000 $finish;

always #1 CLK = ~CLK; // to generate clock from t=0, and T=2 units 

initial 	   // 注意！！！使用non-block赋值和内嵌式时延，可以产生精确的绝对时延 .

   	begin  // 产生测试输入序列,模拟按键－>保持->中断申请(接口电路端)，
   		  // 中断响应-> 片选使能-> 读取信号-> 片选无效-> 中断退出（处理器端）的过程
	    CLK<= 0;
	    RST<= 1;
		RST<= #3 0;
	    
	    COL<= #2 4'b1111;   //no key pressed     
		RD <= 1;
		OE <= 0;
		CS <= 0;

	    COL<= #8 4'b1110; // (from left) a key of 1st col	pressed
	    CS <= #10 1;
		RD <= #11 0;
		RD <= #13 1;
	    CS <= #14 0;
		COL <= #15 4'b1111;	//released the key

		
		COL<= #18 4'b1101; // (from left) a key of 2nd col	pressed
		CS <=#20 1;
		RD<= #21 0;
		RD<= #23 1;
	    CS <=#24 0;
	   	COL <= #25 4'b1111;	//released the key
		
		COL<= #28 4'b1011; // (from left) a key of 3rd col	pressed
		CS <=#30 1;
		RD<= #31 0;
		RD<= #33 1;
	    CS <=#34 0;
		COL <= #35 4'b1111;	//released the key
		
		COL<= #38 4'b0111; // (from left) a key of 4th col	pressed
		CS <=#40 1;
		RD<= #41 0;
		RD<= #43 1;
	    CS <=#44 0;
		COL <= #45 4'b1111;	//released the key
	end 

//键盘扫描示例化
keyscan  uut1(RST,OE,RD,CS,CLK,COL,R,DOUT,INT);
endmodule