muxstr.v

发一个基于ModelSim仿真的Verilog源代码包

module mux_str(out,a,b,sel);
	output out;
	input a,b,sel;
	not gate1(net1,sel);
	and gate2(net2,a,net1);
	and gate3(net3,b,sel);
	or  gate4(out,net2,net3);
endmodule