testformuxstr.v

发一个基于ModelSim仿真的Verilog源代码包

module test_for_muxstr;
reg a,b,s;
mux_str mux1(out,a,b,s);
always
	begin
		$monitor($time,"a=%b  b=%b  s=%b  out=%b",a,b,s,out);
	a=0;b=1;s=0;
	#10 a=1;
	#10 b=0;
	#10 s=1;
	#10 b=1;
	#10 a=0;
  //#10 $finish;
	end
endmodule