convencdja.v

来自「发一个基于ModelSim仿真的Verilog源代码包」· Verilog 代码 · 共 79 行

  `timescale 1ns/10ps
 

//     TOP_ENCODE
//--------------------

module top_encode(clk, rst, dataIn, serialData, parData);

input clk, rst, dataIn;
output serialData;
output [1:0] parData;
wire serialData;
wire [1:0] parData;

conv_encode  conv_encode_1(clk, rst, dataIn, serialData);
ser2par      ser2par_1(clk, rst, serialData, parData); 

endmodule


//     conv_encode
//-------------------------------

module conv_encode(clk, rst, x_unsync, z);
   input clk, rst, x_unsync;
   output z;
   wire x_unsync;
   reg x, z;
   reg u1, u2;
   reg[1:0] ShftReg;

// The encoder shift register and a synchronizing flip-flop.
always@(posedge clk or posedge rst)
 begin: reg_gen
   if (rst)begin
      ShftReg <= 0;
      x <= 0;
     end
   else begin 
      ShftReg <= {x,ShftReg[1]};
      x <= x_unsync;
   end
end

// The MUX 
always@(clk or x or ShftReg)
   begin: output_gen
     u1 = (x^ShftReg[1]^ShftReg[0]); 
     u2 = (x^ShftReg[0]); 
     z = (clk)? u2:u1;    
  end

endmodule

//    ser2par
//-------------------------------

module ser2par(clk, rst,serialData, parData); 
input clk, rst, serialData;
output [1:0] parData;
reg [1:0] parData;
reg serDataLatch;
wire clk, rst, serialData;

// The flip-flops for serial to parallel conversion
always @(posedge clk or posedge rst)
   if (rst) parData <= 0;
   else parData <= {serialData, serDataLatch};

//The latch for serial to parallel conversion  
// synopsys async_set_reset "rst"   
always @(clk or rst or serialData)
   if (rst) serDataLatch <= 0;
    else if (clk) serDataLatch<=serialData;

endmodule