convencdtestbnch.v

发一个基于ModelSim仿真的Verilog源代码包

 `timescale 1ns/10ps
 
module ConvEncdTestBnch;
     parameter n=15;
	 reg clk, rst, dataIn;
     reg [0:n] data; 
     wire serialData;
     wire [1:0] parData;
	 integer I;
	 initial
	  begin
	      I=0;
          dataIn=0;
          data= 16'b0010_1101_0000_0000;//1010_1100_1110_0110;
	      clk=0;
          rst=0;
          rst <= #1 1;
          rst <= #4 0;
          //rst <= #34 1;
          //rst <= #48 0;
	     forever #5 clk=~clk;
	  end

// send in a new value of x every clock cycle
	always @(posedge clk)
	  	begin
	   		if (I==(n+1)) $finish;
// The #1 makes x change 1ns after the clock and never on the clock edge.
	   		dataIn <= #1 data[I];
 			I<=I+1; 
	 	end
 
  top_encode top_encode_1(clk, rst, dataIn, serialData, parData);

  endmodule