clock.vhd

这是一个用vhdl编的多功能电子秒表

library ieee;
  use  ieee.std_logic_1164.all;
  use ieee.std_logic_unsigned.all;
  use ieee.std_logic_arith.all;

entity  clock  is
  port( cp:in std_logic;
		minten:	out std_logic_vector(3 downto 0);
		min	:	out std_logic_vector(3 downto 0);
		secten:	out std_logic_vector(3 downto 0);
		sec:	out std_logic_vector(3 downto 0);
		stop:	in std_logic;
		reset: 	in std_logic;
        lamp:   out std_logic;
        lam:   out std_logic;
        read: in std_logic);
end clock;

architecture a of clock is
signal mten: integer range 0 to 9;
signal m: integer range 0 to 9;
signal sten: integer range 0 to 9;
signal ss: integer range 0 to 9;
signal read_signal:integer range 0 to 3;
signal ta : integer range 0 to 10;
signal tb : integer range 0 to 10;
signal tc : integer range 0 to 10;
signal td : integer range 0 to 10;
signal xa : integer range 0 to 10;
signal xb : integer range 0 to 10;
signal xc : integer range 0 to 10;
signal xd : integer range 0 to 10;
signal stop_signal: std_logic;

begin
-------------------stop_signal---------------
    process(stop)
    begin
    if stop'event and stop='1' then 
       stop_signal<=not stop_signal;
    end if;
    end process;
------------------clock goes------------------
	process(cp)
	begin
		if cp'event and cp='1' then 
			if reset='0' then	
			if stop_signal='1' then
				if ss=9 then
					ss<=0;
					if sten=5 then
						sten<=0;
						if m=9 then
							m<=0;
							if mten=5 then
								mten<=0;
							else mten<=mten+1;
							end if;
						else m<=m+1;
						end if;
					else sten<=sten+1;
					end if;
				else ss<=ss+1;
				end if;
			end if;
			else mten<=0;
				m<=0;
				sten<=0;
				ss<=0;

			end if;
		end if;
  end process;
------------------------------read_signal-----------
process(read)
begin
  if read'event and read='1' then
     
if read_signal=2 then read_signal<=0 ;else read_signal<=read_signal+1 ; end if ;
  end if;
end process;
--------------------record--------------
process(read_signal)
begin
  if stop_signal='1' then  
  case read_signal is
        when 1=> ta<=ss;tb<=sten; tc<=m; td<=mten;lamp<='1';lam<='0';
        when 2=> xa<=ss;xb<=sten; xc<=m; xd<=mten;lam<='1'; lamp<='0';
        when others => lamp<='0' ;lam<='0';
   end case;
end if;
end process;       
------------------------display--------------
process(cp,read_signal)
begin
    case read_signal  is
    when 1=>if stop_signal='0' then
    minten<=conv_std_logic_vector(td,4);
	min<=conv_std_logic_vector(tc,4);
	secten<=conv_std_logic_vector(tb,4);
	sec<=conv_std_logic_vector(ta,4);
          end if;
    when 2=>
           if stop_signal='0' then
    minten<=conv_std_logic_vector(xd,4);
	min<=conv_std_logic_vector(xc,4);
	secten<=conv_std_logic_vector(xb,4);
	sec<=conv_std_logic_vector(xa,4);
          end if;
    when others=>
	minten<=conv_std_logic_vector(mten,4);
	min<=conv_std_logic_vector(m,4);
	secten<=conv_std_logic_vector(sten,4);
	sec<=conv_std_logic_vector(ss,4);
    end case;
end process;
end a;