📄 counter60.rpt
字号:
A: 4/ 96( 4%) 9/ 48( 18%) 0/ 48( 0%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:d:\maxplus2\maxplus2\workplace\vhdl\vhdl0\clock1\counter60.rpt
counter60
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 7 clk
Device-Specific Information:d:\maxplus2\maxplus2\workplace\vhdl\vhdl0\clock1\counter60.rpt
counter60
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 7 clr
Device-Specific Information:d:\maxplus2\maxplus2\workplace\vhdl\vhdl0\clock1\counter60.rpt
counter60
** EQUATIONS **
clk : INPUT;
clr : INPUT;
-- Node name is 'high0'
-- Equation name is 'high0', type is output
high0 = h0;
-- Node name is 'high1'
-- Equation name is 'high1', type is output
high1 = h1;
-- Node name is 'high2'
-- Equation name is 'high2', type is output
high2 = h2;
-- Node name is 'high3'
-- Equation name is 'high3', type is output
high3 = GND;
-- Node name is ':17' = 'h0'
-- Equation name is 'h0', location is LC1_A5, type is buried.
h0 = DFFE( _EQ001, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ001 = _LC3_A5 & !_LC6_A2
# _LC2_A5 & _LC4_A5;
-- Node name is ':16' = 'h1'
-- Equation name is 'h1', location is LC7_A5, type is buried.
h1 = DFFE( _EQ002, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ002 = h1 & _LC2_A10 & _LC4_A5
# !h0 & h1 & _LC4_A5
# h0 & !h1 & !_LC2_A10 & _LC4_A5;
-- Node name is ':15' = 'h2'
-- Equation name is 'h2', location is LC5_A5, type is buried.
h2 = DFFE( _EQ003, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ003 = _LC4_A5 & _LC8_A5
# _LC3_A5 & !_LC6_A2;
-- Node name is 'low0'
-- Equation name is 'low0', type is output
low0 = l0;
-- Node name is 'low1'
-- Equation name is 'low1', type is output
low1 = l1;
-- Node name is 'low2'
-- Equation name is 'low2', type is output
low2 = l2;
-- Node name is 'low3'
-- Equation name is 'low3', type is output
low3 = l3;
-- Node name is ':14' = 'l0'
-- Equation name is 'l0', location is LC2_A2, type is buried.
l0 = DFFE( _EQ004, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ004 = _LC3_A2 & _LC3_A5
# _LC3_A2 & _LC4_A5;
-- Node name is ':13' = 'l1'
-- Equation name is 'l1', location is LC3_A9, type is buried.
l1 = DFFE( _EQ005, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ005 = _LC1_A9 & _LC3_A5
# _LC1_A9 & _LC4_A5;
-- Node name is ':12' = 'l2'
-- Equation name is 'l2', location is LC5_A2, type is buried.
l2 = DFFE( _EQ006, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ006 = _LC3_A5 & _LC4_A2
# _LC4_A2 & _LC4_A5;
-- Node name is ':11' = 'l3'
-- Equation name is 'l3', location is LC1_A2, type is buried.
l3 = DFFE( _EQ007, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ007 = _LC3_A5 & _LC8_A2
# _LC4_A5 & _LC8_A2;
-- Node name is '|LPM_ADD_SUB:431|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_A5', type is buried
_LC6_A5 = LCELL( _EQ008);
_EQ008 = h0 & h1;
-- Node name is ':87'
-- Equation name is '_LC3_A5', type is buried
_LC3_A5 = LCELL( _EQ009);
_EQ009 = h0 & !h1 & h2;
-- Node name is ':165'
-- Equation name is '_LC7_A2', type is buried
!_LC7_A2 = _LC7_A2~NOT;
_LC7_A2~NOT = LCELL( _EQ010);
_EQ010 = l0 & l3
# l2 & l3
# l1 & l3;
-- Node name is ':187'
-- Equation name is '_LC6_A2', type is buried
_LC6_A2 = LCELL( _EQ011);
_EQ011 = l0 & !l1 & !l2 & l3;
-- Node name is ':278'
-- Equation name is '_LC8_A2', type is buried
_LC8_A2 = LCELL( _EQ012);
_EQ012 = l0 & l1 & l2
# !l0 & l3
# l2 & l3
# l1 & l3;
-- Node name is ':287'
-- Equation name is '_LC4_A2', type is buried
_LC4_A2 = LCELL( _EQ013);
_EQ013 = !l1 & l2
# !l0 & l2
# l0 & l1 & !l2 & !l3
# l2 & l3;
-- Node name is ':296'
-- Equation name is '_LC1_A9', type is buried
_LC1_A9 = LCELL( _EQ014);
_EQ014 = !l0 & l1
# l0 & !l1 & !l3
# l1 & l3;
-- Node name is ':460'
-- Equation name is '_LC8_A5', type is buried
_LC8_A5 = LCELL( _EQ015);
_EQ015 = h2 & !_LC6_A5
# !h2 & _LC6_A2 & _LC6_A5 & !_LC7_A2
# h2 & !_LC6_A2
# h2 & _LC7_A2;
-- Node name is ':478'
-- Equation name is '_LC2_A5', type is buried
_LC2_A5 = LCELL( _EQ016);
_EQ016 = h0 & _LC7_A2
# h0 & !_LC6_A2
# !h0 & _LC6_A2 & !_LC7_A2;
-- Node name is '~564~1'
-- Equation name is '~564~1', location is LC2_A10, type is buried.
-- synthesized logic cell
!_LC2_A10 = _LC2_A10~NOT;
_LC2_A10~NOT = LCELL( _EQ017);
_EQ017 = _LC6_A2 & !_LC7_A2;
-- Node name is '~607~1'
-- Equation name is '~607~1', location is LC3_A2, type is buried.
-- synthesized logic cell
_LC3_A2 = LCELL( _EQ018);
_EQ018 = _LC7_A2 & !l0
# !_LC6_A2 & l0 & l3;
-- Node name is '~609~1'
-- Equation name is '~609~1', location is LC4_A5, type is buried.
-- synthesized logic cell
_LC4_A5 = LCELL( _EQ019);
_EQ019 = !h2
# !h0 & !h1;
Project Informationd:\maxplus2\maxplus2\workplace\vhdl\vhdl0\clock1\counter60.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 19,071K
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