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📄 fifoasi.tan.rpt

📁 主要完成数字电视前端信号处理和缓冲作用的verilog源代码
💻 RPT
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; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
+-------------------------------------------------------------+-----------+-----------------------------------+----------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+----------------------------------------------+--------------+
; Type                                                        ; Slack     ; Required Time                     ; Actual Time                      ; From                                                                                                                                    ; To                                                                                                                                        ; From Clock                                   ; To Clock                                     ; Failed Paths ;
+-------------------------------------------------------------+-----------+-----------------------------------+----------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+----------------------------------------------+--------------+
; Worst-case tsu                                              ; 3.340 ns  ; 15.000 ns                         ; 11.660 ns                        ; CE[0]                                                                                                                                   ; dsptoasi:inst40|dsptoasi_dcfifo_8cs:dsptoasi_dcfifo_8cs_component|dsptoasi_altsyncram_bv01:altsyncram1|ram_block30a_15~porta_datain_reg15 ;                                              ; DSPCLK                                       ; 0            ;
; Worst-case tco                                              ; 4.281 ns  ; 15.000 ns                         ; 10.719 ns                        ; 16to8ddf:inst21|lpm_dff4:inst|lpm_ff:lpm_ff_component|dffs[3]                                                                           ; TXDA[3]                                                                                                                                   ; ASICLK                                       ;                                              ; 0            ;
; Worst-case tpd                                              ; 2.803 ns  ; 15.000 ns                         ; 12.197 ns                        ; EA[1]                                                                                                                                   ; dspio[1]                                                                                                                                  ;                                              ;                                              ; 0            ;
; Clock Setup: 'altpll1:inst18|altpll:altpll_component|_clk1' ; 3.241 ns  ; 100.00 MHz ( period = 10.000 ns ) ; 147.95 MHz ( period = 6.759 ns ) ; asitodsp:inst13|dcfifo:dcfifo_component|dcfifo_dv21:auto_generated|alt_synch_pipe_2a3:alt_synch_pipe24|dffpipe_2a3:dffpipe31|dffe34a[5] ; asitodsp:inst13|dcfifo:dcfifo_component|dcfifo_dv21:auto_generated|a_graycounter_i06:a_graycounter8|power_modified_counter_values[0]      ; altpll1:inst18|altpll:altpll_component|_clk1 ; altpll1:inst18|altpll:altpll_component|_clk1 ; 0            ;
; Clock Setup: 'altpll0:inst17|altpll:altpll_component|_clk0' ; 30.974 ns ; 27.00 MHz ( period = 37.037 ns )  ; 164.93 MHz ( period = 6.063 ns ) ; asitodsp:inst|dcfifo:dcfifo_component|dcfifo_dv21:auto_generated|cntr_uu7:cntr4|safe_q[0]                                               ; asitodsp:inst|dcfifo:dcfifo_component|dcfifo_dv21:auto_generated|dffe19a[7]                                                               ; altpll0:inst17|altpll:altpll_component|_clk0 ; altpll0:inst17|altpll:altpll_component|_clk0 ; 0            ;
; Total number of failed paths                                ;           ;                                   ;                                  ;                                                                                                                                         ;                                                                                                                                           ;                                              ;                                              ; 0            ;
+-------------------------------------------------------------+-----------+-----------------------------------+----------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+----------------------------------------------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                 ;
+----------------------------------------------+--------------------+------------+------------------+----------+-----------------------+---------------------+-----------+
; Clock Node Name                              ; Clock Setting Name ; Type       ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ;
+----------------------------------------------+--------------------+------------+------------------+----------+-----------------------+---------------------+-----------+
; altpll1:inst18|altpll:altpll_component|_clk1 ;                    ; PLL output ; 100.0 MHz        ; DSPCLK   ; 1                     ; 1                   ; -1.443 ns ;
; altpll0:inst17|altpll:altpll_component|_clk0 ;                    ; PLL output ; 27.0 MHz         ; ASICLK   ; 1                     ; 1                   ; -1.443 ns ;
; ASICLK                                       ; ASICLK             ; User Pin   ; 27.0 MHz         ; NONE     ; N/A                   ; N/A                 ; N/A       ;
; DSPCLK                                       ; DSPCLK             ; User Pin   ; 100.0 MHz        ; NONE     ; N/A                   ; N/A                 ; N/A       ;
+----------------------------------------------+--------------------+------------+------------------+----------+-----------------------+---------------------+-----------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'altpll1:inst18|altpll:altpll_component|_clk1'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+----------------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                    ; To                                                                                                                                      ; From Clock                                   ; To Clock                                     ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+----------------------------------------------+-----------------------------+---------------------------+-------------------------+
; 3.241 ns                                ; 147.95 MHz ( period = 6.759 ns )                    ; asitodsp:inst13|dcfifo:dcfifo_component|dcfifo_dv21:auto_generated|alt_synch_pipe_2a3:alt_synch_pipe24|dffpipe_2a3:dffpipe31|dffe34a[5] ; asitodsp:inst13|dcfifo:dcfifo_component|dcfifo_dv21:auto_generated|a_graycounter_i06:a_graycounter8|power_modified_counter_values[0]    ; altpll1:inst18|altpll:altpll_component|_clk1 ; altpll1:inst18|altpll:altpll_component|_clk1 ; 10.000 ns                   ; 9.739 ns                  ; 6.498 ns                ;
; 3.241 ns                                ; 147.95 MHz ( period = 6.759 ns )                    ; asitodsp:inst13|dcfifo:dcfifo_component|dcfifo_dv21:auto_generated|alt_synch_pipe_2a3:alt_synch_pipe24|dffpipe_2a3:dffpipe31|dffe34a[5] ; asitodsp:inst13|dcfifo:dcfifo_component|dcfifo_dv21:auto_generated|a_graycounter_i06:a_graycounter8|power_modified_counter_values[1]    ; altpll1:inst18|altpll:altpll_component|_clk1 ; altpll1:inst18|altpll:altpll_component|_clk1 ; 10.000 ns                   ; 9.739 ns                  ; 6.498 ns                ;
; 3.241 ns                                ; 147.95 MHz ( period = 6.759 ns )                    ; asitodsp:inst13|dcfifo:dcfifo_component|dcfifo_dv21:auto_generated|alt_synch_pipe_2a3:alt_synch_pipe24|dffpipe_2a3:dffpipe31|dffe34a[5] ; asitodsp:inst13|dcfifo:dcfifo_component|dcfifo_dv21:auto_generated|a_graycounter_i06:a_graycounter8|power_modified_counter_values[2]    ; altpll1:inst18|altpll:altpll_component|_clk1 ; altpll1:inst18|altpll:altpll_component|_clk1 ; 10.000 ns                   ; 9.739 ns                  ; 6.498 ns                ;
; 3.241 ns                                ; 147.95 MHz ( period = 6.759 ns )                    ; asitodsp:inst13|dcfifo:dcfifo_component|dcfifo_dv21:auto_generated|alt_synch_pipe_2a3:alt_synch_pipe24|dffpipe_2a3:dffpipe31|dffe34a[5] ; asitodsp:inst13|dcfifo:dcfifo_component|dcfifo_dv21:auto_generated|a_graycounter_i06:a_graycounter8|power_modified_counter_values[3]    ; altpll1:inst18|altpll:altpll_component|_clk1 ; altpll1:inst18|altpll:altpll_component|_clk1 ; 10.000 ns                   ; 9.739 ns                  ; 6.498 ns                ;
; 3.241 ns                                ; 147.95 MHz ( period = 6.759 ns )                    ; asitodsp:inst13|dcfifo:dcfifo_component|dcfifo_dv21:auto_generated|alt_synch_pipe_2a3:alt_synch_pipe24|dffpipe_2a3:dffpipe31|dffe34a[5] ; asitodsp:inst13|dcfifo:dcfifo_component|dcfifo_dv21:auto_generated|a_graycounter_i06:a_graycounter8|power_modified_counter_values[4]    ; altpll1:inst18|altpll:altpll_component|_clk1 ; altpll1:inst18|altpll:altpll_component|_clk1 ; 10.000 ns                   ; 9.739 ns                  ; 6.498 ns                ;
; 3.241 ns                                ; 147.95 MHz ( period = 6.759 ns )                    ; asitodsp:inst13|dcfifo:dcfifo_component|dcfifo_dv21:auto_generated|alt_synch_pipe_2a3:alt_synch_pipe24|dffpipe_2a3:dffpipe31|dffe34a[5] ; asitodsp:inst13|dcfifo:dcfifo_component|dcfifo_dv21:auto_generated|a_graycounter_i06:a_graycounter8|power_modified_counter_values[5]    ; altpll1:inst18|altpll:altpll_component|_clk1 ; altpll1:inst18|altpll:altpll_component|_clk1 ; 10.000 ns                   ; 9.739 ns                  ; 6.498 ns                ;
; 3.241 ns                                ; 147.95 MHz ( period = 6.759 ns )                    ; asitodsp:inst13|dcfifo:dcfifo_component|dcfifo_dv21:auto_generated|alt_synch_pipe_2a3:alt_synch_pipe24|dffpipe_2a3:dffpipe31|dffe34a[5] ; asitodsp:inst13|dcfifo:dcfifo_component|dcfifo_dv21:auto_generated|a_graycounter_i06:a_graycounter8|power_modified_counter_values[6]    ; altpll1:inst18|altpll:altpll_component|_clk1 ; altpll1:inst18|altpll:altpll_component|_clk1 ; 10.000 ns                   ; 9.739 ns                  ; 6.498 ns                ;
; 3.241 ns                                ; 147.95 MHz ( period = 6.759 ns )                    ; asitodsp:inst13|dcfifo:dcfifo_component|dcfifo_dv21:auto_generated|alt_synch_pipe_2a3:alt_synch_pipe24|dffpipe_2a3:dffpipe31|dffe34a[5] ; asitodsp:inst13|dcfifo:dcfifo_component|dcfifo_dv21:auto_generated|a_graycounter_i06:a_graycounter8|power_modified_counter_values[7]    ; altpll1:inst18|altpll:altpll_component|_clk1 ; altpll1:inst18|altpll:altpll_component|_clk1 ; 10.000 ns                   ; 9.739 ns                  ; 6.498 ns                ;
; 3.241 ns                                ; 147.95 MHz ( period = 6.759 ns )                    ; asitodsp:inst13|dcfifo:dcfifo_component|dcfifo_dv21:auto_generated|alt_synch_pipe_2a3:alt_synch_pipe24|dffpipe_2a3:dffpipe31|dffe34a[5] ; asitodsp:inst13|dcfifo:dcfifo_component|dcfifo_dv21:auto_generated|a_graycounter_i06:a_graycounter8|parity                              ; altpll1:inst18|altpll:altpll_component|_clk1 ; altpll1:inst18|altpll:altpll_component|_clk1 ; 10.000 ns                   ; 9.739 ns                  ; 6.498 ns                ;
; 3.827 ns                                ; 162.00 MHz ( period = 6.173 ns )                    ; asitodsp:inst13|dcfifo:dcfifo_component|dcfifo_dv21:auto_generated|a_graycounter_i06:a_graycounter8|power_modified_counter_values[1]    ; asitodsp:inst13|dcfifo:dcfifo_component|dcfifo_dv21:auto_generated|a_graycounter_i06:a_graycounter8|power_modified_counter_values[0]    ; altpll1:inst18|altpll:altpll_component|_clk1 ; altpll1:inst18|altpll:altpll_component|_clk1 ; 10.000 ns                   ; 9.739 ns                  ; 5.912 ns                ;

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