fifoasi.tan.rpt

来自「主要完成数字电视前端信号处理和缓冲作用的verilog源代码」· RPT 代码 · 共 200 行 · 第 1/5 页

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+--------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                   ;
+-------------------------------------------------------+--------------------+------+--------+
; Option                                                ; Setting            ; From ; To     ;
+-------------------------------------------------------+--------------------+------+--------+
; Device name                                           ; EP1C4F324C8        ;      ;        ;
; Timing Models                                         ; Production         ;      ;        ;
; Number of source nodes to report per destination node ; 10                 ;      ;        ;
; Number of destination nodes to report                 ; 10                 ;      ;        ;
; Number of paths to report                             ; 200                ;      ;        ;
; Run Minimum Analysis                                  ; Off                ;      ;        ;
; Use Minimum Timing Models                             ; Off                ;      ;        ;
; Report IO Paths Separately                            ; Off                ;      ;        ;
; Clock Analysis Only                                   ; Off                ;      ;        ;
; Default hold multicycle                               ; Same as Multicycle ;      ;        ;
; Cut paths between unrelated clock domains             ; On                 ;      ;        ;
; Cut off read during write signal paths                ; On                 ;      ;        ;
; Cut off clear and preset signal paths                 ; On                 ;      ;        ;
; Cut off feedback from I/O pins                        ; On                 ;      ;        ;
; tpd Requirement                                       ; 15ns               ;      ;        ;
; Minimum tpd Requirement                               ; 5ns                ;      ;        ;
; th Requirement                                        ; 5ns                ;      ;        ;
; tsu Requirement                                       ; 15ns               ;      ;        ;
; tco Requirement                                       ; 15ns               ;      ;        ;
; Minimum tco Requirement                               ; 5ns                ;      ;        ;
; Ignore Clock Settings                                 ; Off                ;      ;        ;
; Analyze latches as synchronous elements               ; Off                ;      ;        ;
; Clock Settings                                        ; Asiclk             ;      ; ASICLK ;
; Clock Settings                                        ; Dspclk             ;      ; DSPCLK ;
+-------------------------------------------------------+--------------------+------+--------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+