fen.par

verilog

Constraints file: fen.pcf

Loading device database for application Par from file "fen_map.ncd".
   "fen" is an NCD, version 2.38, device xc2s50, package pq208, speed -6
Loading device for application Par from file 'v50.nph' in environment E:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-06-19.


Resolved that GCLKIOB <f> must be placed at site P185.
Resolved that IOB <f4t> must be placed at site P120.
Resolved that IOB <f5t> must be placed at site P126.
Resolved that IOB <reset> must be placed at site P95.


Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs             3 out of 140     2%
      Number of LOCed External IOBs    3 out of 3     100%

   Number of SLICEs                    5 out of 768     1%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:9896a7) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.
Phase 5.8 (Checksum:98a5bb) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file fen.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 40 unrouted;       REAL time: 0 secs 

Phase 2: 35 unrouted;       REAL time: 0 secs 

Phase 3: 10 unrouted;       REAL time: 0 secs 

Phase 4: 0 unrouted;       REAL time: 0 secs 

Total REAL time to Router completion: 0 secs 
Total CPU time to Router completion: 0 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|           f_BUFGP          |  Global  |    5   |  0.005     |  0.381      |
+----------------------------+----------+--------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 105


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        0.868
   The MAXIMUM PIN DELAY IS:                               1.811
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   0.918

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
          33           7           0           0           0           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 0 secs 
Total CPU time to PAR completion: 0 secs 

Peak Memory Usage:  45 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file fen.ncd.


PAR done.