uartrx.tdf

来自「verilog编写的全功能串口」· TDF 代码 · 共 71 行

include "lpm_dff";
include "lpm_counter";
subdesign uartrx
(
	sysclk			:	input;		-- system clock
	inbaud			:	input;		-- baud rate clock * 8
	rxd				:	input;
	d[7..0]			:	output;
	valid			:	output;
	clk				:	output;
	sample			:	output;
	start_stop_err	:	output;
)
variable
	pulse			:	machine with states (idle,wait);
	process			:	machine with states (start,shift);

	fn_count		:	lpm_counter with (lpm_width=6,lpm_direction="UP");

	d[7..0]			:	dffe;
	data[9..0]		:	dffe;
begin
	-- sample inbaud signal
	pulse.clk=global(sysclk);
	case pulse is
		when idle =>
			if inbaud then
				clk=vcc;
				pulse=wait;
			end if;
		when wait =>
			if not inbaud then
				pulse=idle;
			end if;
	end case;

	-- attach sync counter and data shift register
	fn_count.clock=sysclk;
	fn_count.clk_en=clk;
	data[8..0]=data[9..1];
	data[9]=rxd;
	data[].clk=sysclk;
	d[]=data[8..1];
	d[].clk=sysclk;

	-- attach process FSM
	process.clk=sysclk;
	case process is
		when start =>
			fn_count.sclr=vcc;
			if not rxd then
				process=shift;
			end if;
		when shift =>
			fn_count.cnt_en=vcc;
			if fn_count.q[]==39 then
				start_stop_err=((not data[9]) or data[0]);
				valid=vcc;
				d[].ena=vcc;
				process=start;
			end if;
	end case;

	-- decode sample times
	case fn_count.q[] is
		when 2,6,10,14,18,22,26,30,34,38 =>
			sample=vcc;
			data[].ena=clk;
	end case;
end;