uarttx.tdf

verilog编写的全功能串口

include "lpm_counter";
subdesign uarttx
(
	sysclk			:	input;	-- global system clock
	txd				:	output;
	inbaud			:	input;	-- baudrate * 8
	busy			:	output;
	d[7..0]			:	input;
	/wr				:	input;	-- write signal
	cs				:	input;	-- chip select
	clk				:	output;
	start			:	output;
)
variable
	divclk			:	machine with states (edge,wait);
	pulse			:	machine with states (low,high);
	process			:	machine with states (idle,send0,send1,send2,send3,send4);

	fn_div			:	lpm_counter with (lpm_width=2,lpm_direction="UP");

	txd				:	dff;
	data[9..0]		:	dffe;

	clk				:	node;
begin
	data[].clk=global(sysclk);
	txd.clk=sysclk;
	fn_div.clock=sysclk;

	-- handle dividing the inbaud clock
	divclk.clk=sysclk;
	case divclk is
		when edge =>
			if inbaud then
				fn_div.cnt_en=vcc;
				divclk=wait;
			end if;
		when wait =>
			if not inbaud then
				divclk=edge;
			end if;
	end case;

	-- handle the shift clocking enable
	pulse.clk=sysclk;
	case pulse is
		when low =>
			if (fn_div.q[]==0) then
				clk=vcc;
				pulse=high;
			end if;
		when high =>
			if (fn_div.q[1]!=0) then
				pulse=low;
			end if;
	end case;

	-- handle sending the data
	process.clk=sysclk;
	case process is
		when idle =>
			txd=vcc;
			if (not /wr) and cs then
				process=send0;
			end if;
		when send0 =>
			fn_div.sclr=vcc;
			txd=vcc;
			data[]=(vcc,d[],gnd);
			data[].ena=vcc;
			process=send1;
		when send1 =>
			start=vcc;
			if /wr then
				process=send2;
			end if;
		when send2 =>
			txd=vcc;
			if not inbaud then
				process=send3;
			else
				fn_div.sclr=vcc;
				process=send4;
			end if;
		when send3 =>
			txd=vcc;
			if inbaud then
				fn_div.sclr=vcc;
				process=send4;
			end if;
		when send4 =>
			busy=vcc;
			data[8..0]=data[9..1];
			data[].ena=clk;
			if (data[]==0) then
				txd=vcc;
				process=idle;
			else
				txd=data[0];
			end if;
	end case;
end;