miniuart.tdf

来自「verilog编写的全功能串口」· TDF 代码 · 共 51 行

include "uartbaud";
include "uartrx";
include "uarttx";
parameters
(
	crystal=20000000,
	baudrate=9600,
	genclk="YES"
);
subdesign miniuart
(
	clock			:	input;
	d_in[7..0]		:	input;
	d_out[7..0]		:	output;
	/int			:	output;
	/wr				:	input;
	cs				:	input;
	rxd				:	input;
	txd				:	output;
	inbaud			:	input;
	outbaud			:	output;
	busy			:	output;
)
variable
	if genclk=="YES" generate
	fn_baud			:	uartbaud with (crystal=crystal,baudrate=baudrate*8);
	end generate;
	fn_uart_rx		:	uartrx;
	fn_uart_tx		:	uarttx;
begin
	fn_uart_rx.sysclk=global(clock);
	if genclk=="YES" generate
		fn_baud.sysclk=clock;
		fn_uart_rx.inbaud=fn_baud.baud;
		fn_uart_tx.inbaud=fn_baud.baud;
		outbaud=fn_baud.baud;
	else generate
		fn_uart_rx.inbaud=inbaud;
		fn_uart_tx.inbaud=inbaud;
	end generate;
	fn_uart_rx.rxd=rxd;
	d_out[]=fn_uart_rx.d[];
	fn_uart_tx.sysclk=clock;
	/int=not fn_uart_rx.valid;
	busy=fn_uart_tx.busy;
	txd=fn_uart_tx.txd;
	fn_uart_tx.cs=cs;
	fn_uart_tx./wr=/wr;
	fn_uart_tx.d[]=d_in[];
end;