octart.tdf

来自「verilog编写的全功能串口」· TDF 代码 · 共 39 行

include "uartbaud";
include "miniuart";
subdesign octart
(
	c/d				:	input;
	a[2..0]			:	input;
	d[7..0]			:	bidir;
	cs				:	input;
	/wr				:	input;
	/rd				:	input;
	/int[7..0]		:	output;
	clock			:	input;
	txd[7..0]		:	output;
	rxd[7..0]		:	input;
)
variable
	fn_baud			:	uartbaud with (crystal=20000000,baudrate=9600*8);
	fn_uart[7..0]	:	miniuart with (crystal=20000000,genclk="NO");

	d_node[7..0]	:	node;
begin
	fn_baud.sysclk=global(clock);
	for i in 7 to 0 generate
		fn_uart[i].clock=clock;
		fn_uart[i].inbaud=fn_baud.baud;
		fn_uart[i]./wr=/wr;
		fn_uart[i]./rd=/rd;
		/int[i]=fn_uart[i]./int;
		txd[i]=fn_uart[i].txd;
		fn_uart[i].rxd=rxd[i];
		d[i]=tri(d_node[i],not /rd and not c/d and cs);
		fn_uart[i].d_in[]=d[];
		if (i==a[]) and not c/d and cs then
			fn_uart[i].cs=vcc;
			d_node[]=fn_uart[i].d_out[];
		end if;
	end generate;
end;