📄 clock.rpt
字号:
A7 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 16/22( 72%)
A8 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 2/22( 9%)
A9 7/ 8( 87%) 3/ 8( 37%) 2/ 8( 25%) 0/2 0/2 9/22( 40%)
A10 3/ 8( 37%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 0/22( 0%)
A11 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 12/22( 54%)
A13 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 4/22( 18%)
A15 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 6/22( 27%)
A16 3/ 8( 37%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 7/22( 31%)
A17 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 0/2 3/22( 13%)
A19 6/ 8( 75%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 10/22( 45%)
A20 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 0/2 6/22( 27%)
A22 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 8/22( 36%)
A23 7/ 8( 87%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 9/22( 40%)
B1 7/ 8( 87%) 1/ 8( 12%) 1/ 8( 12%) 2/2 0/2 9/22( 40%)
B3 5/ 8( 62%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 4/22( 18%)
B4 8/ 8(100%) 2/ 8( 25%) 5/ 8( 62%) 1/2 0/2 3/22( 13%)
B5 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
B6 6/ 8( 75%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 3/22( 13%)
B9 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
B10 2/ 8( 25%) 0/ 8( 0%) 1/ 8( 12%) 2/2 0/2 0/22( 0%)
B11 8/ 8(100%) 2/ 8( 25%) 5/ 8( 62%) 1/2 0/2 4/22( 18%)
B12 8/ 8(100%) 2/ 8( 25%) 6/ 8( 75%) 0/2 0/2 9/22( 40%)
C1 6/ 8( 75%) 3/ 8( 37%) 0/ 8( 0%) 1/2 0/2 0/22( 0%)
C5 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 0/22( 0%)
C11 5/ 8( 62%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 0/22( 0%)
C14 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 1/2 0/2 3/22( 13%)
C18 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 4/22( 18%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 40/60 ( 66%)
Total logic cells used: 201/576 ( 34%)
Total embedded cells used: 0/48 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.34/4 ( 83%)
Total fan-in: 673/2304 ( 29%)
Total input pins required: 6
Total input I/O cell registers required: 0
Total output pins required: 40
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 201
Total flipflops required: 77
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 48/ 576 ( 8%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 7 8 6 8 6 8 8 8 7 3 8 0 0 2 0 8 3 8 0 6 8 0 8 7 0 127/0
B: 7 0 5 8 1 6 0 0 1 2 8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 46/0
C: 6 0 0 0 1 0 0 0 0 0 5 0 0 0 8 0 0 0 8 0 0 0 0 0 0 28/0
Total: 20 8 11 16 8 14 8 8 8 5 21 8 0 2 8 8 3 8 8 6 8 0 8 7 0 201/0
Device-Specific Information: c:\max2work\clock.rpt
clock
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
91 - - - -- INPUT ^ 0 0 0 4 change
39 - - - -- INPUT G ^ 0 0 0 5 clk
90 - - - -- INPUT G ^ 0 0 0 2 clk_1k
40 - - - -- INPUT G ^ 0 0 0 0 mode
89 - - - -- INPUT G ^ 0 0 0 0 start_end
38 - - - -- INPUT G ^ 0 0 0 3 turn
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: c:\max2work\clock.rpt
clock
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
8 - - A -- OUTPUT 0 1 0 0 alert
26 - - - 23 OUTPUT 0 1 0 0 hour0
77 - - - 01 OUTPUT 0 1 0 0 hour1
70 - - A -- OUTPUT 0 1 0 0 hour2
28 - - - 20 OUTPUT 0 1 0 0 hour3
43 - - - 12 OUTPUT 0 1 0 0 hour4
94 - - - 19 OUTPUT 0 1 0 0 hour5
33 - - - 15 OUTPUT 0 1 0 0 hour6
10 - - A -- OUTPUT 0 1 0 0 hour7
5 - - A -- OUTPUT 0 1 0 0 LD_alert
15 - - B -- OUTPUT 0 1 0 0 LD_hour
62 - - B -- OUTPUT 0 1 0 0 LD_min
58 - - C -- OUTPUT 0 1 0 0 LD_10ms
68 - - A -- OUTPUT 0 1 0 0 min0
7 - - A -- OUTPUT 0 1 0 0 min1
9 - - A -- OUTPUT 0 1 0 0 min2
86 - - - 09 OUTPUT 0 1 0 0 min3
46 - - - 10 OUTPUT 0 1 0 0 min4
79 - - - 02 OUTPUT 0 1 0 0 min5
71 - - A -- OUTPUT 0 1 0 0 min6
69 - - A -- OUTPUT 0 1 0 0 min7
87 - - - 12 OUTPUT 0 1 0 0 ms_num0
55 - - C -- OUTPUT 0 1 0 0 ms_num1
56 - - C -- OUTPUT 0 1 0 0 ms_num2
6 - - A -- OUTPUT 0 1 0 0 sec0
13 - - B -- OUTPUT 0 1 0 0 sec1
14 - - B -- OUTPUT 0 1 0 0 sec2
61 - - B -- OUTPUT 0 1 0 0 sec3
64 - - B -- OUTPUT 0 1 0 0 sec4
65 - - B -- OUTPUT 0 1 0 0 sec5
63 - - B -- OUTPUT 0 1 0 0 sec6
16 - - B -- OUTPUT 0 1 0 0 sec7
57 - - C -- OUTPUT 0 1 0 0 _10ms_num0
20 - - C -- OUTPUT 0 1 0 0 _10ms_num1
34 - - - 14 OUTPUT 0 1 0 0 _10ms_num2
21 - - C -- OUTPUT 0 1 0 0 _10ms_num3
31 - - - 17 OUTPUT 0 1 0 0 _10ms_num4
23 - - C -- OUTPUT 0 1 0 0 _10ms_num5
19 - - C -- OUTPUT 0 1 0 0 _10ms_num6
22 - - C -- OUTPUT 0 1 0 0 _10ms_num7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\max2work\clock.rpt
clock
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - B 04 AND2 0 2 0 1 |lpm_add_sub:1175|addcore:adder|:55
- 8 - B 04 AND2 0 3 0 1 |lpm_add_sub:1175|addcore:adder|:59
- 8 - B 11 AND2 0 2 0 1 |lpm_add_sub:1176|addcore:adder|:55
- 7 - A 04 AND2 0 2 0 1 |lpm_add_sub:1177|addcore:adder|:55
- 8 - A 04 AND2 0 3 0 1 |lpm_add_sub:1177|addcore:adder|:59
- 7 - A 08 AND2 0 2 0 1 |lpm_add_sub:1180|addcore:adder|:55
- 8 - A 08 AND2 0 3 0 1 |lpm_add_sub:1180|addcore:adder|:59
- 4 - A 22 AND2 0 2 0 1 |lpm_add_sub:1183|addcore:adder|:55
- 7 - A 22 AND2 0 3 0 1 |lpm_add_sub:1183|addcore:adder|:59
- 4 - A 15 OR2 ! 0 2 0 3 |lpm_add_sub:1184|addcore:adder|:55
- 7 - A 20 AND2 0 2 0 1 |lpm_add_sub:1186|addcore:adder|:55
- 8 - A 20 AND2 0 3 0 1 |lpm_add_sub:1186|addcore:adder|:59
- 2 - A 17 OR2 ! 0 2 0 3 |lpm_add_sub:1187|addcore:adder|:55
- 7 - C 18 AND2 0 2 0 1 |lpm_add_sub:1190|addcore:adder|:55
- 7 - C 14 AND2 0 2 0 1 |lpm_add_sub:1191|addcore:adder|:55
- 8 - C 14 AND2 0 3 0 1 |lpm_add_sub:1191|addcore:adder|:59
- 3 - C 01 DFFE + 0 2 0 3 m2 (:61)
- 5 - C 01 DFFE + 0 1 0 4 m1 (:62)
- 1 - C 01 DFFE + 0 0 0 5 m0 (:63)
- 2 - C 01 AND2 0 3 0 21 :64
- 1 - B 06 DFFE + 0 0 0 4 fm1 (:72)
- 2 - B 06 DFFE + 0 0 0 2 fm0 (:73)
- 5 - B 06 AND2 1 1 0 2 :74
- 4 - C 01 AND2 0 3 0 21 :80
- 5 - B 01 OR2 0 3 0 4 :92
- 4 - B 01 DFFE + 0 2 0 2 loop31 (:112)
- 3 - B 01 DFFE + 0 2 0 2 loop30 (:113)
- 7 - B 01 DFFE + 0 3 0 1 num30 (:127)
- 1 - B 10 DFFE + 0 0 0 1 clk_2Hz (:134)
- 5 - B 10 DFFE 0 1 0 9 clk_1Hz (:137)
- 5 - B 04 AND2 s 0 3 0 1 ~147~1
- 1 - B 09 AND2 1 1 0 1 :150
- 2 - B 04 OR2 0 4 0 6 :151
- 1 - B 11 AND2 0 4 0 6 :155
- 2 - B 01 AND2 s 0 2 0 3 ~189~1
- 4 - B 04 DFFE 0 4 0 5 sec17 (:201)
- 1 - B 04 DFFE 0 4 0 5 sec16 (:202)
- 3 - B 04 DFFE 0 4 0 6 sec15 (:203)
- 6 - B 04 DFFE 0 3 0 7 sec14 (:204)
- 7 - B 11 DFFE 0 4 0 4 sec13 (:205)
- 3 - B 11 DFFE 0 4 0 5 sec12 (:206)
- 5 - B 11 DFFE 0 3 0 6 sec11 (:207)
- 6 - B 11 DFFE 1 2 0 7 sec10 (:208)
- 6 - B 01 DFFE 1 3 0 1 minclk (:220)
- 1 - B 01 OR2 1 3 0 9 :225
- 6 - A 04 OR2 s ! 0 3 0 4 ~227~1
- 2 - A 06 OR2 ! 0 4 0 7 :239
- 2 - A 04 DFFE 0 4 0 3 min17 (:286)
- 4 - A 04 DFFE 0 4 0 7 min16 (:287)
- 1 - A 04 DFFE 0 4 0 5 min15 (:288)
- 5 - A 04 DFFE 0 3 0 9 min14 (:289)
- 7 - A 06 DFFE 0 4 0 5 min13 (:290)
- 4 - A 06 DFFE 0 4 0 5 min12 (:291)
- 3 - A 06 DFFE 0 3 0 6 min11 (:292)
- 5 - A 06 DFFE 0 1 0 8 min10 (:293)
- 3 - B 03 OR2 0 3 0 4 :307
- 2 - B 03 DFFE + 0 2 0 2 loop11 (:327)
- 1 - B 03 DFFE + 0 2 0 2 loop10 (:328)
- 5 - B 03 DFFE + 0 3 0 1 num10 (:342)
- 4 - B 03 OR2 1 2 0 8 :349
- 6 - A 08 OR2 ! 0 4 0 4 :351
- 8 - A 02 OR2 ! 0 4 0 7 :363
- 1 - A 08 DFFE 0 4 0 3 amin7 (:410)
- 4 - A 08 DFFE 0 4 0 5 amin6 (:411)
- 5 - A 08 DFFE 0 4 0 5 amin5 (:412)
- 3 - A 08 DFFE 0 3 0 7 amin4 (:413)
- 2 - A 02 DFFE 0 4 0 4 amin3 (:414)
- 1 - A 02 DFFE 0 4 0 5 amin2 (:415)
- 3 - A 02 DFFE 0 3 0 6 amin1 (:416)
- 8 - A 03 DFFE 0 1 0 7 amin0 (:417)
- 4 - B 06 AND2 ! 0 2 0 4 :429
- 3 - A 05 OR2 1 2 0 4 :439
- 2 - A 05 DFFE + 0 2 0 2 loop41 (:459)
- 1 - A 05 DFFE + 0 2 0 2 loop40 (:460)
- 4 - A 05 DFFE + 0 3 0 1 num40 (:474)
- 3 - A 04 DFFE 0 5 0 1 hclk (:482)
- 8 - A 05 OR2 1 3 0 8 :487
- 5 - A 15 OR2 s 0 4 0 1 ~489~1
- 2 - A 15 OR2 ! 0 4 0 5 :489
- 1 - A 15 OR2 ! 0 4 0 5 :501
- 7 - A 15 AND2 s 0 2 0 3 ~538~1
- 6 - A 22 DFFE 0 4 0 3 hour17 (:548)
- 3 - A 22 DFFE 0 4 0 4 hour16 (:549)
- 2 - A 22 DFFE 0 4 0 5 hour15 (:550)
- 1 - A 22 DFFE 0 3 0 6 hour14 (:551)
- 3 - A 15 DFFE 0 4 0 4 hour13 (:552)
- 6 - A 15 DFFE 0 3 0 5 hour12 (:553)
- 8 - A 15 DFFE 0 3 0 4 hour11 (:554)
- 1 - A 13 DFFE 0 1 0 5 hour10 (:555)
- 5 - A 23 OR2 1 2 0 4 :568
- 3 - A 23 DFFE + 0 2 0 2 loop21 (:588)
- 2 - A 23 DFFE + 0 2 0 2 loop20 (:589)
- 6 - A 23 DFFE + 0 3 0 1 num20 (:603)
- 1 - A 23 OR2 1 2 0 8 :610
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