clock.rpt

verilog编写实用多功能电子表

Project Information                                      c:\max2work\clock.rpt

MAX+plus II Compiler Report File
Version 10.12 09/21/2001
Compiled: 02/23/2005 09:17:00

Copyright (C) 1988-2001 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input Output Bidir  Memory  Memory  			 LCs
POF       Device          Pins  Pins   Pins   Bits % Utilized  LCs  % Utilized

clock     EP1K10TC100-1    6      40     0    0         0  %    201      34 %

User Pins:                 6      40     0  



Project Information                                      c:\max2work\clock.rpt

** PROJECT COMPILATION MESSAGES **

Warning: Flipflop ':602' stuck at GND
Warning: Flipflop ':473' stuck at GND
Warning: Flipflop ':126' stuck at GND
Warning: Flipflop ':341' stuck at GND


** PROJECT TIMING MESSAGES **

Info: Timing SNF for project is based on DMF version 10.12 for device EP1K10TC100-1


Project Information                                      c:\max2work\clock.rpt

** FILE HIERARCHY **



|lpm_add_sub:1173|
|lpm_add_sub:1173|addcore:adder|
|lpm_add_sub:1173|altshift:result_ext_latency_ffs|
|lpm_add_sub:1173|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1173|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1174|
|lpm_add_sub:1174|addcore:adder|
|lpm_add_sub:1174|altshift:result_ext_latency_ffs|
|lpm_add_sub:1174|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1174|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1175|
|lpm_add_sub:1175|addcore:adder|
|lpm_add_sub:1175|altshift:result_ext_latency_ffs|
|lpm_add_sub:1175|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1175|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1176|
|lpm_add_sub:1176|addcore:adder|
|lpm_add_sub:1176|altshift:result_ext_latency_ffs|
|lpm_add_sub:1176|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1176|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1177|
|lpm_add_sub:1177|addcore:adder|
|lpm_add_sub:1177|altshift:result_ext_latency_ffs|
|lpm_add_sub:1177|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1177|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1178|
|lpm_add_sub:1178|addcore:adder|
|lpm_add_sub:1178|altshift:result_ext_latency_ffs|
|lpm_add_sub:1178|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1178|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1179|
|lpm_add_sub:1179|addcore:adder|
|lpm_add_sub:1179|altshift:result_ext_latency_ffs|
|lpm_add_sub:1179|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1179|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1180|
|lpm_add_sub:1180|addcore:adder|
|lpm_add_sub:1180|altshift:result_ext_latency_ffs|
|lpm_add_sub:1180|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1180|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1181|
|lpm_add_sub:1181|addcore:adder|
|lpm_add_sub:1181|altshift:result_ext_latency_ffs|
|lpm_add_sub:1181|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1181|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1182|
|lpm_add_sub:1182|addcore:adder|
|lpm_add_sub:1182|altshift:result_ext_latency_ffs|
|lpm_add_sub:1182|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1182|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1183|
|lpm_add_sub:1183|addcore:adder|
|lpm_add_sub:1183|altshift:result_ext_latency_ffs|
|lpm_add_sub:1183|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1183|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1184|
|lpm_add_sub:1184|addcore:adder|
|lpm_add_sub:1184|altshift:result_ext_latency_ffs|
|lpm_add_sub:1184|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1184|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1185|
|lpm_add_sub:1185|addcore:adder|
|lpm_add_sub:1185|altshift:result_ext_latency_ffs|
|lpm_add_sub:1185|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1185|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1186|
|lpm_add_sub:1186|addcore:adder|
|lpm_add_sub:1186|altshift:result_ext_latency_ffs|
|lpm_add_sub:1186|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1186|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1187|
|lpm_add_sub:1187|addcore:adder|
|lpm_add_sub:1187|altshift:result_ext_latency_ffs|
|lpm_add_sub:1187|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1187|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1188|
|lpm_add_sub:1188|addcore:adder|
|lpm_add_sub:1188|altshift:result_ext_latency_ffs|
|lpm_add_sub:1188|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1188|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1189|
|lpm_add_sub:1189|addcore:adder|
|lpm_add_sub:1189|altshift:result_ext_latency_ffs|
|lpm_add_sub:1189|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1189|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1190|
|lpm_add_sub:1190|addcore:adder|
|lpm_add_sub:1190|altshift:result_ext_latency_ffs|
|lpm_add_sub:1190|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1190|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1191|
|lpm_add_sub:1191|addcore:adder|
|lpm_add_sub:1191|altshift:result_ext_latency_ffs|
|lpm_add_sub:1191|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1191|altshift:oflow_ext_latency_ffs|


Device-Specific Information:                             c:\max2work\clock.rpt
clock

***** Logic for device 'clock' compiled without errors.




Device: EP1K10TC100-1

ACEX 1K Configuration Scheme: Passive Serial

Device Options:
    User-Supplied Start-Up Clock               = OFF
    Auto-Restart Configuration on Frame Error  = OFF
    Release Clears Before Tri-States           = OFF
    Enable Chip_Wide Reset                     = OFF
    Enable Chip-Wide Output Enable             = OFF
    Enable INIT_DONE Output                    = OFF
    JTAG User Code                             = 7f
    MultiVolt I/O                              = OFF
    Enable Lock Output                         = OFF

                                                                   
                                      s                            
                  R R R R     R       t       R R   R R R   R      
                  E E E E     E       a   m   E E   E E E   E      
                  S S S S     S V c c r   s   S S   S S S   S   ^  
                  E E E E   h E C h l t   _   E E V E E E   E h D  
                # R R R R   o R C a k _   n m R R C R R R m R o A  
                T V V V V G u V I n _ e G u i V V C V V V i V u T  
                C E E E E N r E N g 1 n N m n E E I E E E n E r A  
                K D D D D D 5 D T e k d D 0 3 D D O D D D 5 D 1 0  
              ----------------------------------------------------_ 
             / 100  98  96  94  92  90  88  86  84  82  80  78  76   |_ 
            /     99  97  95  93  91  89  87  85  83  81  79  77    | 
^CONF_DONE |  1                                                    75 | ^DCLK 
     ^nCEO |  2                                                    74 | ^nCE 
      #TDO |  3                                                    73 | #TDI 
     VCCIO |  4                                                    72 | VCCINT 
  LD_alert |  5                                                    71 | min6 
      sec0 |  6                                                    70 | hour2 
      min1 |  7                                                    69 | min7 
     alert |  8                                                    68 | min0 
      min2 |  9                                                    67 | VCCIO 
     hour7 | 10                                                    66 | GND 
       GND | 11                                                    65 | sec5 
    VCCINT | 12                                                    64 | sec4 
      sec1 | 13                   EP1K10TC100-1                    63 | sec6 
      sec2 | 14                                                    62 | LD_min 
   LD_hour | 15                                                    61 | sec3 
      sec7 | 16                                                    60 | VCCINT 
     VCCIO | 17                                                    59 | GND 
       GND | 18                                                    58 | LD_10ms 
_10ms_num6 | 19                                                    57 | _10ms_num0 
_10ms_num1 | 20                                                    56 | ms_num2 
_10ms_num3 | 21                                                    55 | ms_num1 
_10ms_num7 | 22                                                    54 | ^MSEL0 
_10ms_num5 | 23                                                    53 | ^MSEL1 
      #TMS | 24                                                    52 | VCCINT 
  ^nSTATUS | 25                                                    51 | ^nCONFIG 
           |      27  29  31  33  35  37  39  41  43  45  47  49  _| 
            \   26  28  30  32  34  36  38  40  42  44  46  48  50   | 
             \----------------------------------------------------- 
                h R h R R _ R h _ V G V t c m G G h V R m R R R R  
                o E o E E 1 E o 1 C N C u l o N N o C E i E E E E  
                u S u S S 0 S u 0 C D C r k d D D u C S n S S S S  
                r E r E E m E r m I   _ n   e _   r I E 4 E E E E  
                0 R 3 R R s R 6 s N   C       C   4 O R   R R R R  
                  V   V V _ V   _ T   K       K       V   V V V V  
                  E   E E n E   n     L       L       E   E E E E  
                  D   D D u D   u     K       K       D   D D D D  
                          m     m                                  
                          4     2                                  


N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.

^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin. 
@ = Special-purpose pin. 
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration.  JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant. 


Device-Specific Information:                             c:\max2work\clock.rpt
clock

** RESOURCE USAGE **

Logic                Column       Row                                   
Array                Interconnect Interconnect         Clears/     External  
Block   Logic Cells  Driven       Driven       Clocks  Presets   Interconnect
A1       7/ 8( 87%)   2/ 8( 25%)   1/ 8( 12%)    0/2    0/2      16/22( 72%)   
A2       8/ 8(100%)   0/ 8(  0%)   5/ 8( 62%)    1/2    0/2      10/22( 45%)   
A3       6/ 8( 75%)   0/ 8(  0%)   4/ 8( 50%)    1/2    0/2      10/22( 45%)   
A4       8/ 8(100%)   0/ 8(  0%)   5/ 8( 62%)    1/2    0/2       3/22( 13%)   
A5       6/ 8( 75%)   0/ 8(  0%)   2/ 8( 25%)    1/2    0/2       7/22( 31%)   
A6       8/ 8(100%)   0/ 8(  0%)   6/ 8( 75%)    1/2    0/2       8/22( 36%)