no3.rpt

verilog编写实用多功能电子表

40:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
41:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
42:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
43:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
44:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
45:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
46:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
47:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
48:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
49:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
50:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
51:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
52:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:                               c:\max2work\no3.rpt
no3

** EQUATIONS **

in0      : INPUT;
in1      : INPUT;
in2      : INPUT;

-- Node name is 'out0' 
-- Equation name is 'out0', type is output 
out0     =  _LC6_B22;

-- Node name is 'out1' 
-- Equation name is 'out1', type is output 
out1     =  _LC1_B22;

-- Node name is 'out2' 
-- Equation name is 'out2', type is output 
out2     =  _LC8_B22;

-- Node name is 'out3' 
-- Equation name is 'out3', type is output 
out3     =  _LC3_B22;

-- Node name is 'out4' 
-- Equation name is 'out4', type is output 
out4     =  _LC5_B22;

-- Node name is 'out5' 
-- Equation name is 'out5', type is output 
out5     =  _LC7_B22;

-- Node name is 'out6' 
-- Equation name is 'out6', type is output 
out6     =  _LC4_B22;

-- Node name is 'out7' 
-- Equation name is 'out7', type is output 
out7     =  _LC2_B22;

-- Node name is ':124' 
-- Equation name is '_LC2_B22', type is buried 
_LC2_B22 = LCELL( _EQ001);
  _EQ001 =  in0 &  in1 &  in2;

-- Node name is ':125' 
-- Equation name is '_LC4_B22', type is buried 
_LC4_B22 = LCELL( _EQ002);
  _EQ002 = !in0 &  in1 &  in2;

-- Node name is ':126' 
-- Equation name is '_LC7_B22', type is buried 
_LC7_B22 = LCELL( _EQ003);
  _EQ003 =  in0 & !in1 &  in2;

-- Node name is ':127' 
-- Equation name is '_LC5_B22', type is buried 
_LC5_B22 = LCELL( _EQ004);
  _EQ004 = !in0 & !in1 &  in2;

-- Node name is ':128' 
-- Equation name is '_LC3_B22', type is buried 
_LC3_B22 = LCELL( _EQ005);
  _EQ005 =  in0 &  in1 & !in2;

-- Node name is ':129' 
-- Equation name is '_LC8_B22', type is buried 
_LC8_B22 = LCELL( _EQ006);
  _EQ006 = !in0 &  in1 & !in2;

-- Node name is ':130' 
-- Equation name is '_LC1_B22', type is buried 
_LC1_B22 = LCELL( _EQ007);
  _EQ007 =  in0 & !in1 & !in2;

-- Node name is ':131' 
-- Equation name is '_LC6_B22', type is buried 
_LC6_B22 = LCELL( _EQ008);
  _EQ008 = !in0 & !in1 & !in2;



Project Information                                        c:\max2work\no3.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:07
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:08


Memory Allocated
-----------------

Peak memory allocated during compilation  = 49,194K