ahdlcnt.tdf

verilog编写实用多功能电子表

SUBDESIGN ahdlcnt
(
	clk, load, ena, clr, d[15..0]	: INPUT;
	q[15..0]							: OUTPUT;
)
VARIABLE
	count[15..0]						: DFF;
BEGIN
	count[].clk = clk;
	count[].clrn = !clr;

	IF load THEN
		count[].d = d[];
	ELSIF ena THEN
		count[].d = count[].q + 1;
	ELSE
		count[].d = count[].q;
	END IF;

	q[] = count[];
END;