reg_out.tdf

来自「verilog编写实用多功能电子表」· TDF 代码 · 共 13 行

SUBDESIGN reg_out
(
	clk, load, d[7..0]	: INPUT;
	q[7..0]				: OUTPUT;
)
VARIABLE
	q[7..0]				: DFFE;	   % also declared as outputs %
BEGIN
	q[].clk = clk;
	q[].ena = load;
	q[] = d[];
END;