default2.tdf

来自「verilog编写实用多功能电子表」· TDF 代码 · 共 28 行

SUBDESIGN default2
(
	a, b, c							: INPUT;
	select_a, select_b, select_c	: INPUT;
	wire_or, wire_and				: OUTPUT;
)
BEGIN
	DEFAULTS
		wire_or = GND;
		wire_and = VCC;
	END DEFAULTS;

	IF select_a THEN
		wire_or = a;
		wire_and = a;
	END IF;

	IF select_b THEN
		wire_or = b;
		wire_and = b;
	END IF;

	IF select_c THEN
		wire_or = c;
		wire_and = c;
	END IF;
END;