ver_butterworth.html

来自「verilog的入门级别的例子（转载）」· HTML 代码 · 共 333 行 · 第 1/2 页

<P>Butterworth filters are also known as "maximally flat" filters because they have no passband ripple. They also have a monotonic response in both the stopband and passband. Butterworth filters tradeoff roll off steepness for their no-ripple characteristic.</P>

<p>The complexity of calculating the result of the Butterworth filter can be greatly reduced if the filter is broken down into several second order systems known as biquads. The higher the filter order, the better its characteristics, but the more complex it is to implement. By breaking a complex filter into biquads, this complexity is greatly reduced.</p>

<p>The transfer function of a Butterworth filter is shown below:</p>

<img src="images/ver-butterworth_eqn.gif" alt="" width="172" height="59" border="0">

<p>Since the coefficient for the <i>z</i><font size="-1"><SUP>-1</SUP></font> term is twice that of the other terms in the numerator, it can be implemented using a series of shift and add operations. This optimization reduces the number of multipliers in each biquad to just two. A gain factor is introduced, but this can be corrected at the end of the cascade chain through a single multiplier.</p>

<p>This Butterworth infinite impulse response (IIR) filter design uses two biquads to implement a 4<SUP><font size="-1">th</font></SUP> order filter in Stratix<sup>&#153;</sup>. The input is a 12-bit signed integer, the filter coefficients are scaled to 10 bits, and the output is 21 bits wide. See <a href="/literature/an/an215.pdf"><i>AN 215: Implementing High Performance DSP Functions in Stratix Devices</i></a> for details of the implementation.</p>

<p>Download the files used in this example:</p>
<ul><li><a href="/patches/examples/verilog/butterworth.zip">Download butterworth.zip</a>
<li><a href="../download/butterworth_vlog_readme-v1.0.0p1.txt">Download Butterworth IIR Design Example README File</a> 
</ul>

<p>Files in the download include:</p>

<ul>
<li>butterworth_iir.v - Top-level design file
<li>butterworth_iir_biquad.v - Second-order biquad structure
<li>two_mult_add.v - Multiply-add function implemented using altmult_add Megafunction
<li>fb_adder.v - Adder in the feedback path implemented using the lpm_add_sub Megafunction
<li>ff_adder1.v, ff_adder2.v - Adders in the feedforward path implemented using the lpm_add_sub Megafunction
<li>gain_blk.v - Gain block compensates for the gain factor at the end of the filtering stage
<li>butter_iir.m - MATLAB script to verify functionality of design
</ul>

<p>Figure 1 contains the butterworth_iir top-level block diagram.</p>


<p><b><i>Figure 1. butterworth_iir Top-Level Block Diagram</i></b></p>
<img src="images/ver-butterworth_fig1.gif" alt="Figure 1. butterworth_iir Top-Level Block Diagram" width="543" height="149" border="0">

<p>Table 1 shows the Butterworth IIR design example port listing.</p>

<br>
<table width="100%" border="1" cellspacing="0" cellpadding="2">
  <tr> 
    <td colspan="3"><b><i>Table 1. Butterworth IIR Design Example Port Listing</i></b></td>
  </tr>
  <tr bgcolor="#000099"> 
    <td><b><font color="#FFFFFF">Port Name</font></b></td>
    <td align="center"><b><font color="#FFFFFF">Type</font></b></td>
    <td align="center"><b><font color="#FFFFFF">Description</font></b></td>
  </tr>
  <tr> 
    <td valign="top"><b>x[11..0]</b></td>
    <td valign="top" align="center">Input</td>
    <td valign="top">The input is a 12-bit signed integer. This is the x[n] time 
      sample represented as an 18-bit signed input.</td>
  </tr>
  <tr> 
    <td valign="top"><b>clk</b></td>
    <td valign="top" align="center">Input</td>
    <td valign="top">Clock</td>
  </tr>
  <tr> 
    <td valign="top"><b>clken</b></td>
    <td valign="top" align="center">Input</td>
    <td valign="top">Clock enable</td>
  </tr>
  <tr> 
    <td valign="top"><b>reset</b></td>
    <td valign="top" align="center">Input</td>
    <td valign="top">Reset</td>
  </tr>
  <tr> 
    <td valign="top"><b>result[20..0]</b></td>
    <td valign="top" align="center">Output</td>
    <td valign="top">Output of the IIR filter. This is 21 bits wide in the 17.4 
      signed binary fractional (SBF) format.</td>
  </tr>
</table>
<br>
<HR noshade>
<p>For more information on using this example, go to:</p>
<ul><li><a href="verilog.html">How to Use Verilog HDL Examples</a>
<li><a href="/literature/an/an215.pdf"><i>AN 215: Implementing High Performance DSP Functions in Stratix Devices</i></a>
</ul>
<HR noshade>
<h2>Feedback</h2>

<p>Did this information help you?</p>

<p>If no, please log onto <a href="https://mysupport.altera.com/eservice/">mySupport</a> to file a technical request or enhancement.</p>

<p><hr noshade><p></p>

<font size="-1">Altera does not warrant that this solution will work for the customer's intended purpose and disclaims all liability for use of or reliance on the solution.</font>




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