ver_base_fir.html

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<H2>Verilog HDL: Basic FIR Filter</H2>


<P>This document describes the implementation of a basic finite impulse response (FIR) filter in Stratix<sup>&#153;</sup> devices. FIR filters are commonly used in digital signal processing (DSP) systems.</P>

<p>The basic structure of a FIR filter consists of a series of multiplications followed by an addition. A FIR filter operation can be represented by the following equation:</p>

<img src="images/ver-base_fir_eqn.gif" alt="" width="153" height="58" border="0">

<p>This is where <i>x</i>(<i>n</i>) represents the sequence of input samples, <i>h</i>(<i>n</i>) represents the filter coefficients and L is the number of taps. A sample FIR filter with <i>L</i>=8 is shown in Figure 1.In Figure 1, eight samples of the input are used. Hence, it is called an 8-tap filter. Each of the registers provides a unit sample delay. The delayed inputs are multiplied with their respective filter coefficients and added together to produce the output.</p>

<p><b><i>Figure 1. Basic FIR Filter</i></b></p>
<img src="images/ver-base_fir_fig1.jpg" alt="Figure 1. Basic FIR Filter" width="343" height="146" border="0">

<p>This particular design example has eight taps with 18-bit input samples and filter coefficients. Since a single DSP block can support up to four taps with 18-bit inputs, this design requires two DSP blocks. The input data is loaded serially into the DSP block. The shiftin/shiftout register chains inside the DSP blocks are used to create the appropriate delays. The filter coefficients are loaded from ROM implemented in TriMatrix<sup>&#153;</sup> memory blocks. See <i><a href="/literature/an/an215.pdf">AN 215: Implementing High-Performance DSP Functions in Stratix Devices</a></i> for details of the implementation.</p>

<p>Download the files used in this example:</p>
<ul>
<li><a href="/patches/examples/verilog/base_fir.zip">Download base_fir.zip</a>
<li><a href="../download/base_fir_vlog_readme-v1.0.0p1.txt">Download Basic FIR Filter Design Example README File</a>
</ul>
<p>Files included in download:</p>
<ul>
<li>basic_fir.v - Top-level design file
<li>bmult_add.v - Multiply-add function implementation using altmult_add megafunction
<li>badder.v - Adder to sum all eight multiply-add operations
<li>bbasic_fir.m - MATLAB script to verify functionality of design
</ul>
<p>Figure 2 illustrates the basic_fir top-level block diagram.</p>

<p><b><i>Figure 2. basic_fir Top-Level Block Diagram</i></b></p>
<img src="images/ver-base_fir_fig2.gif" alt="Figure 2. basic_fir Top-Level Block Diagram" width="526" height="135" border="0">

<p>Table 1 shows the basic FIR filter design example port listing.</p>

<table width="100%" border="1" cellspacing="0" cellpadding="2">
  <tr> 
    <td colspan="3"><b><i>Table 1. Basic FIR Filter Design Example Port Listing</i></b></td>
  </tr>
  <tr bgcolor="#000099"> 
    <td><b><font color="#FFFFFF">Port Name</font></b></td>
    <td align="center"><b><font color="#FFFFFF">Type</font></b></td>
    <td align="center"><b><font color="#FFFFFF">Description</font></b></td>
  </tr>
  <tr> 
    <td valign="top"><b>data_in[17..0]</b></td>
    <td valign="top" align="center">Input</td>
    <td valign="top">The input is an 18-bit signed integer that is shifted in 
      serially using the shift registers of the DSP block.</td>
  </tr>
  <tr> 
    <td valign="top"><b>clock</b></td>
    <td valign="top" align="center">Input</td>
    <td valign="top">Clock</td>
  </tr>
  <tr> 
    <td valign="top"><b>clk_ena</b></td>
    <td valign="top" align="center">Input</td>
    <td valign="top">Clock-enable</td>
  </tr>
  <tr> 
    <td valign="top"><b>reset</b></td>
    <td valign="top" align="center">Input</td>
    <td valign="top">Asynchronous reset</td>
  </tr>
  <tr> 
    <td valign="top"><b>fir_result[37..0]</b></td>
    <td valign="top" align="center">Output</td>
    <td valign="top">Output of the FIR filter</td>
  </tr>
</table>
<br>
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<p>For more information on using this example, go to:</p>
<ul><li><a href="verilog.html">How to Use Verilog HDL Examples</a>
<li><a href="/literature/an/an215.pdf"><i>AN 215: Implementing High Performance DSP Functions in Stratix Devices</i></a>
</ul>
<HR noshade>
<h2>Feedback</h2>

<p>Did this information help you?</p>

<p>If no, please log onto <a href="https://mysupport.altera.com/eservice/">mySupport</a> to file a technical request or enhancement.</p>

<p><hr noshade><p></p>

<font size="-1">Altera does not warrant that this solution will work for the customer's intended purpose and disclaims all liability for use of or reliance on the solution.</font>




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