ver_tdm_fir.html

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<P>A time domain multiplexed finite impulse response (FIR) filter is clocked n times as fast as the sample rate in order to reuse the same hardware. Since the same circuitry is being reused, this technique saves logic resources.</P>

<p>Figure 1 shows an 8-tap time domain multiplexed FIR filter with a time domain multiplex factor of two. Since the factor is two, only four multipliers are required to implement the 8-tap filter. In the first cycle of the 2x clock, the result of multiplying the input with the first four coefficients is computed; in the second cycle, the result of multiplying the input with the remaining four coefficients is computed. At the end of two cycles of 2x clock, these results are added to generate the overall output. The delay introduced by the register at the output ensures that the two results are aligned properly.</p>

<p><b><i>Figure 1. Block Diagram of Filter with Time Domain Multiplex Factor of n=2</i></b></p>
<img src="images/ver-tdm_fir_fig1.gif" alt="Figure 1. Block Diagram of Filter with Time Domain Multiplex Factor of n=2" width="426" height="140" border="0">

<p>This design example describes the design of an 8-tap time domain multiplexed FIR filter with 18-bit coefficient and input resolution. Both the data and the coefficients are loaded in parallel. See <i><a href="/literature/an/an215.pdf">AN 215: Implementing High Performance DSP Functions in Stratix Devices</a></i> for details.</p>

<p>Download the files used in this example:</p>
<ul>
<li><a href="/patches/examples/verilog/tdm_fir.zip">Download tdm_fir.zip</a>
<li><a href="../download/tdm_fir_vlog_readme-v1.0.0p1.txt">Download Time Domain Multiplexed FIR Filter Design Example README File</a>
</ul>

<p>Files in the download include:</p>

<ul>
<li>tdm_fir.v - Top-level design file
<li>clk_pll.v - PLL to generate 1x and 2x clock
<li>sr_shift_taps.v - Shift register implemented using altshift_taps Megafunction
<li>mult_add.v - Multiply-add function implementation using altmult_add Megafunction
<li>ext_adder.v - Adder to sum all eight multiply-add operations
<li>rom0.v, rom1.v, rom2.v, rom3.v - ROM used to store coefficients
<li>tdm_fir.m - MATLAB script to verify functionality of design
</ul>
<p>Figure 2 illustrates the tdm_fir top-level block diagram.</p>

<p><b><i>Figure 2. tdm_fir Top-Level Block Diagram</i></b></p>
<img src="images/ver-tdm_fir_fig2.gif" alt="Figure 2. tdm_fir Top-Level Block Diagram" width="524" height="139" border="0">
<p>Table 1 shows the Time Domain Multiplex FIR filter design example port listing.</p>

<table width="100%" border="1" cellspacing="0" cellpadding="2">
  <tr> 
    <td colspan="3"><b><i>Table 1. Time Domain Multiplexed FIR Filter Design Example 
      Port Listing Listing</i></b></td>
  </tr>
  <tr bgcolor="#000099"> 
    <td><b><font color="#FFFFFF">Port Name</font></b></td>
    <td align="center"><b><font color="#FFFFFF">Type</font></b></td>
    <td align="center"><b><font color="#FFFFFF">Description</font></b></td>
  </tr>
  <tr> 
    <td valign="top"><b>x0[17..0]</b></td>
    <td valign="top" align="center">Input</td>
    <td valign="top">Signed 18-bit input data shifted in serially using the shift 
      register within the DSP block</td>
  </tr>
  <tr> 
    <td valign="top"><b>clk</b></td>
    <td valign="top" align="center">Input</td>
    <td valign="top">Clock</td>
  </tr>
  <tr> 
    <td valign="top"><b>clken</b></td>
    <td valign="top" align="center">Input</td>
    <td valign="top">Clock enable</td>
  </tr>
  <tr> 
    <td valign="top"><b>reset</b></td>
    <td valign="top" align="center">Input</td>
    <td valign="top">Reset</td>
  </tr>
  <tr> 
    <td valign="top"><b>load_data</b></td>
    <td valign="top" align="center">Output</td>
    <td valign="top">When asserted, the filter is ready to accept data on the 
      x0 port</td>
  </tr>
  <tr> 
    <td valign="top"><b>tdm_result[38..0]</b></td>
    <td valign="top" align="center">Output</td>
    <td valign="top">Output of the Time Domain Multiplexed FIR filter</td>
  </tr>
</table>
<br>
<HR noshade>

<p>For more information on using this example, go to:</p>
<ul><li><a href="verilog.html">How to Use Verilog HDL Examples</a>
<li><a href="/literature/an/an215.pdf"><i>AN 215: Implementing High Performance DSP Functions in Stratix Devices</i></a>
</ul>

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<font size="-1">Altera does not warrant that this solution will work for the customer's intended purpose and disclaims all liability for use of or reliance on the solution.</font>






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