ver_twod_fir.html

来自「verilog的入门级别的例子（转载）」· HTML 代码 · 共 346 行 · 第 1/2 页

<p>All of the operations mentioned above involve transformation of the input image. This can be presented as the convolution of the two-dimensional input image,<i> x(m,n)</i> with the impulse response of the transform,<i> f(k,l)</i>, resulting in <i>y(m,n)</i>, which is the output image. The basic equation is shown in Figure&nbsp;1.</p>

<p><b><i>Figure 1: Transformation of Input Image</i></b></p>
<img src="images/ver-twod_fir_eqn.gif" alt="" width="248" height="67" border="0">

<p>The <i>f(k,l)</i> function refers to the matrix of filter coefficients. Depending on the type of operation and the choice of the convolutional kernel or mask, <i>f(k,l)</i> is different.</p>

<p>This 3x3 two-dimensional FIR filter design takes in an 8x8 input image with gray pixel values ranging from 0-255 (8-bit) and outputs an 8x8 output image. The output needs to be scaled back to the grayscale range if necessary. See <i><a href="/literature/an/an215.pdf">Application Note 215: Implementing High Performance DSP Functions in Stratix<sup>&#153;</sup> Devices</a></i> for details about implementation.</p>

<p>Download the files used in this example:</p>
<ul><li><a href="/patches/examples/verilog/two_d_fir.zip">Download two_d_fir.zip</a>
<li><a href="../download/two_d_fir_vlog_readme-v1.0.0p1.txt">Download Two-Dimensional FIR Filter Design Example README File </a>
</ul>

<p>Files in the download include:</p>

<ul>
<li>two_d_filter.v - Top-level design file
<li>control.v - Provides RAM control signals to interleave data across three RAM blocks
<li>buffer.v - Stores input image in three separate RAM blocks using M512
<li>mux_ram_row.v - Checks for edge pixels and uses free boundary condition
<li>filter.v - Implements nine multiply-add operations in parallel using DSP blocks
<li>two_d_fir.m - MATLAB script using the 'conv2' utility to verify the functionality of design
</ul>

<p>Figure 2 shows the two_d_filter top-level block diagram.</p>

<p><b><i>Figure 2. two_d_filter Top-Level Block Diagram</i></b></p>
<p><img src="images/ver-twod_fir_fig1.gif" alt="Figure 2. two_d_filter Top-Level Block Diagram" width="509" height="293" border="0"></p>

<p>Table 1 contains the two-dimensional FIR filter design example port listing.</p>
<br>
<table width="100%" border="1" cellspacing="0" cellpadding="2">
  <tr> 
    <td colspan="3"><b><i>Table 1. Two-Dimensional FIR Filter Design Example Port 
      Listing</i></b></td>
  </tr>
  <tr bgcolor="#000099"> 
    <td><b><font color="#FFFFFF">Port Name</font></b></td>
    <td align="center"><b><font color="#FFFFFF">Type</font></b></td>
    <td align="center"><b><font color="#FFFFFF">Description</font></b></td>
  </tr>
  <tr> 
    <td valign="top"><b>data[7..0]</b></td>
    <td valign="top" align="center">Input</td>
    <td valign="top">The input is an 8-bit unsigned grayscale value (0-255). Data 
      is fed in serially starting from the top left pixel, moving horizontally 
      on a row-by-row basis.</td>
  </tr>
  <tr> 
    <td valign="top"><b>coefx_x[8..0]</b></td>
    <td valign="top" align="center">Input</td>
    <td valign="top">Filter coefficients are 9-bit signed integers</td>
  </tr>
  <tr> 
    <td valign="top"><b>clk</b></td>
    <td valign="top" align="center">Input</td>
    <td valign="top">Clock</td>
  </tr>
  <tr> 
    <td valign="top"><b>clken</b></td>
    <td valign="top" align="center">Input</td>
    <td valign="top">Clock enable</td>
  </tr>
  <tr> 
    <td valign="top"><b>aclr</b></td>
    <td valign="top" align="center">Input</td>
    <td valign="top">Asynchronous clear</td>
  </tr>
  <tr> 
    <td valign="top"><b>data_valid</b></td>
    <td valign="top" align="center">Input</td>
    <td valign="top">If data_valid is high, the filter starts operating on the 
      information available on the data[] port. Otherwise, the filter is idle. 
      The data_valid port needs to be asserted throughout the entire stream of 
      64 inputs.</td>
  </tr>
  <tr> 
    <td valign="top"><b>result[20..0]</b></td>
    <td valign="top" align="center">Output</td>
    <td valign="top">Output of the two-dimensional FIR filter needs to be scaled 
      back to the grayscale range if necessary.</td>
  </tr>
</table>
<br>
<HR noshade>
<p>For more information on using this example, go to:</p>
<ul><li><a href="verilog.html">How to Use Verilog HDL Examples</a>
<li><a href="/literature/an/an215.pdf"><i>AN 215: Implementing High Performance DSP Functions in Stratix Devices</i></a>
</ul>
<HR noshade>
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<p><hr noshade><p></p>

<font size="-1">Altera does not warrant that this solution will work for the customer's intended purpose and disclaims all liability for use of or reliance on the solution.</font>




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