ver_base_iir.html

来自「verilog的入门级别的例子（转载）」· HTML 代码 · 共 337 行 · 第 1/2 页

<P>An infinite impulse response (IIR) filter is a recursive filter where the current output depends on previous outputs. The basic equation is shown below:</P>

<img src="images/ver-base_iir_eqn.gif" alt="" width="251" height="56" border="0">

<p>This is where n represents the order of the filter, and the ai and bi terms represent the coefficients of the filter, which consequently determine the filter characteristics. The feedback feature makes IIR filters useful in high-data throughput applications that require low hardware usage. However, the feedback adds complexity to the filter design as it introduces phase distortion and finite word length effects that may cause instability. Careful design consideration must be given to avoid unbounded conditions.</p>

<p>This becomes more critical as the filter order increases. To prevent overflow or instability, the transfer function is divided into second order filters called biquads. This is represented in the figure below as cascaded transfer functions.</p>

<img src="images/ver-base_iir_fig.gif" alt="" width="418" height="70" border="0">

<p>These biquads can be individually scaled and cascaded, which minimizes quantization and recursive accumulation errors.</p>

<p>This IIR filter design uses two biquads to implement a fourth-order filter 
  in Stratix<sup>&#153;</sup>. The input is a 13-bit signed integer, the filter 
  coefficients are scaled to 10 bits, and the output is 38 bits wide. See <a href="/literature/an/an215.pdf"><i>AN 215: Implementing High Performance DSP Functions in Stratix Devices</i></a> 
  for details of the implementation.</p>

<p>Download the files used in this example: </p>

<ul>
<li><a href="/patches/examples/verilog/iir.zip">Download iir.zip</a>
<li><a href="../download/iir_vlog_readme-v1.0.0p1.txt">Download Basic IIR Filter Design Example README File </a>

</ul>
<p>Files in the download include:</p>
<ul>
<li>base_iir.v - Top-level design file
<li>base_iir_biquad.v - Second-order biquad structure
<li>four_mult_add.v - Multiply-add function implemented using altmult_add Megafunction
<li>two_mult_add.v - Multiply-add function implemented using altmult_add Megafunction
<li>adder.v - Adder to store the intermediate feedback values implemented using logic cells
<li>basic_iir.m - MATLAB script to verify functionality of design
</ul>
<p>Figure 1 contains the base_iir top-level block diagram.</p>


<p><b><i>Figure 1. base_iir Top-Level Block Diagram</i></b></p>
<img src="images/ver-base_iir_fig1.gif" alt="Figure 1. base_iir Top-Level Block Diagram" width="542" height="139" border="0">
<br>
<p>Table 1 shows the basic IIR design example port listing.</p>
<br>
<br>
<table width="100%" border="1" cellspacing="0" cellpadding="2">
  <tr> 
    <td colspan="3"><b><i>Table 1. Basic FIR Filter Design Example Port Listing</i></b></td>
  </tr>
  <tr bgcolor="#000099"> 
    <td><b><font color="#FFFFFF">Port Name</font></b></td>
    <td align="center"><b><font color="#FFFFFF">Type</font></b></td>
    <td align="center"><b><font color="#FFFFFF">Description</font></b></td>
  </tr>
  <tr> 
    <td valign="top"><b>x[12..0]</b></td>
    <td valign="top" align="center">Input</td>
    <td valign="top">The input is a 13-bit signed integer. This is the x[n] time 
      sample represented as an 18?bit signed input.</td>
  </tr>
  <tr> 
    <td valign="top"><b>clk</b></td>
    <td valign="top" align="center">Input</td>
    <td valign="top">Clock</td>
  </tr>
  <tr> 
    <td valign="top"><b>clken</b></td>
    <td valign="top" align="center">Input</td>
    <td valign="top">Clock enable</td>
  </tr>
  <tr> 
    <td valign="top"><b>reset</b></td>
    <td valign="top" align="center">Input</td>
    <td valign="top">Reset</td>
  </tr>
  <tr> 
    <td valign="top"><b>result[37..0]</b></td>
    <td valign="top" align="center">Output</td>
    <td valign="top">Output of the IIR filter. This is 38 bits wide in the 24.14 
      signed binary fractional (SBF) format.</td>
  </tr>
</table>
<br>
<HR noshade>
<p>For more information on using this example, go to:</p>
<ul><li><a href="verilog.html">How to Use Verilog HDL Examples</a>
<li><a href="/literature/an/an215.pdf"><i>AN 215: Implementing High Performance DSP Functions in Stratix Devices</i></a>
</ul>
<HR noshade>
<h2>Feedback</h2>

<p>Did this information help you?</p>

<p>If no, please log onto <a href="https://mysupport.altera.com/eservice/">mySupport</a> to file a technical request or enhancement.</p>

<p><hr noshade><p></p>

<font size="-1">Altera does not warrant that this solution will work for the customer's intended purpose and disclaims all liability for use of or reliance on the solution.</font>




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