ver_dct.html

verilog的入门级别的例子（转载）

<P>Similar to discrete fourier transform (DFT), discrete cosine transform (DCT) is a function that maps the input signal or image from spatial domain to frequency domain. DCT transforms the input into a linear combination of weighted basis functions. These basis functions are the frequency component of the input data.</P>

<p>The two-dimensional DCT is just a one-dimensional DCT applied twice, once in the x direction, and again in the y direction. When you apply the DCT to an input image, it yields a matrix of weighted values corresponding to how much of each basis function is present in the original image. For most images, much of the signal energy lies at low frequencies; these appear in the upper-left corner of the DCT. The lower-right values represent higher frequencies, and are often small - small enough to be neglected with little visible distortion.</p>

<p>With an input image, <i>x(m,n)</i>, the coefficients for the output image, <i>Y(p,q)</i>, are:</p>
<img src="images/ver-dct_eqn.gif" alt="" width="452" height="184" border="0">

<p>This serial implementation of the 8x8 two-dimensional DCT design takes in an 8x8 input image with gray pixel values ranging from 0-255 (8-bit) and outputs an 8x8 output image transform. Appropriate scaling needs to be applied to the completed transform, but this can be combined with the quantization stage, which often follows a DCT.</p>

<p>See <i><a href="/literature/an/an215.pdf">AN 215: Implementing High-Performance DSP Functions in Stratix<sup>&#153;</sup> Devices</a></i> for details of the implementation.</p>

<p>Download the files used in this example:</p>
<ul><li><a href="/patches/examples/verilog/two_d_dct_serial.zip">Download two_d_dct_serial.zip</a>
<li><a href="../download/two_d_dct_serial_vlog_readme-v1.0.0p1.txt">Download DCT Design Example README File</a> 

</ul>

<p>Files in the download include:</p>

<ul>
<li>two_d_dct.v - Top-level design file
<li>row_dct.v - Process the data using one-dimensional DCT on a row-by-row basis
<li>column_dct.v - Process the data using one-dimensional DCT on a column-by-column basis
<li>transpose_matrix.v - Stores the partial transform from the row-processing stage, and reorders the data for the column-processing stage
<li>dct_2d.m - MATLAB script to verify the functionality of the design
</ul>

<p>Figure 1 contains the two_d_dct top-level block diagram.</p>
<p><b><i>Figure 1. two_d_dct Top-Level Block Diagram</i></b></p>
<img src="images/ver-dct_fig1.gif" alt="Figure 1. two_d_dct Top-Level Block Diagram" width="540" height="148" border="0">

<p>Table 1 contains the DCT design example port listings.</p>

<br>
<table width="100%" border="1" cellspacing="0" cellpadding="2">
  <tr> 
    <td colspan="3"><b><i>Table 1. DCT Design Example Port Listing</i></b></td>
  </tr>
  <tr bgcolor="#000099"> 
    <td><b><font color="#FFFFFF">Port Name</font></b></td>
    <td align="center"><b><font color="#FFFFFF">Type</font></b></td>
    <td align="center"><b><font color="#FFFFFF">Description</font></b></td>
  </tr>
  <tr> 
    <td valign="top"><b>serial_data[7..0]</b></td>
    <td valign="top" align="center">Input</td>
    <td valign="top">The input is an 8-bit unsigned pixel value from the 8x8 input 
      image. Data is fed into the block serially starting from the top left pixel, 
      moving horizontally on a row-by-row basis.</td>
  </tr>
  <tr> 
    <td valign="top"><b>clk</b></td>
    <td valign="top" align="center">Input</td>
    <td valign="top">Clock</td>
  </tr>
  <tr> 
    <td valign="top"><b>clken</b></td>
    <td valign="top" align="center">Input</td>
    <td valign="top">Clock enable. If clken is high, the function will start to 
      calculate the discrete cosine transform based on the input serial data. 
      This signal has to remain high throughout all 64-input data.</td>
  </tr>
  <tr> 
    <td valign="top"><b>aclr</b></td>
    <td valign="top" align="center">Input</td>
    <td valign="top">Asynchronous clear</td>
  </tr>
  <tr> 
    <td valign="top"><b>dct_out[21..0]</b></td>
    <td valign="top" align="center">Output</td>
    <td valign="top">The DCT output is in the 14:8 signed binary fractional format</td>
  </tr>
  <tr> 
    <td valign="top"><b>data_valid</b></td>
    <td valign="top" align="center">Output</td>
    <td valign="top">Indicates the output is ready. The signal will remain high 
      while all 64 outputs are piped out.</td>
  </tr>
</table>
<br>
<HR noshade>
<p>For more information on using this example, go to:</p>
<ul><li><a href="verilog.html">How to Use Verilog HDL Examples</a>
<li><a href="/literature/an/an215.pdf"><i>AN 215: Implementing High Performance DSP Functions in Stratix Devices</i></a>
</ul>
<HR noshade>
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<p><hr noshade><p></p>

<font size="-1">Altera does not warrant that this solution will work for the customer's intended purpose and disclaims all liability for use of or reliance on the solution.</font>




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