decl7s.rpt

7段数码显示译码器

A2       : INPUT;
A3       : INPUT;

-- Node name is 'LED7S0' 
-- Equation name is 'LED7S0', type is output 
LED7S0   =  _LC6_A22;

-- Node name is 'LED7S1' 
-- Equation name is 'LED7S1', type is output 
LED7S1   =  _LC8_A22;

-- Node name is 'LED7S2' 
-- Equation name is 'LED7S2', type is output 
LED7S2   =  _LC3_A19;

-- Node name is 'LED7S3' 
-- Equation name is 'LED7S3', type is output 
LED7S3   =  _LC4_A22;

-- Node name is 'LED7S4' 
-- Equation name is 'LED7S4', type is output 
LED7S4   =  _LC8_A24;

-- Node name is 'LED7S5' 
-- Equation name is 'LED7S5', type is output 
LED7S5   =  _LC1_A19;

-- Node name is 'LED7S6' 
-- Equation name is 'LED7S6', type is output 
LED7S6   =  _LC4_A19;

-- Node name is '~251~1' 
-- Equation name is '~251~1', location is LC4_A23, type is buried.
-- synthesized logic cell 
_LC4_A23 = LCELL( _EQ001);
  _EQ001 = !A1 & !A2 &  A3;

-- Node name is ':263' 
-- Equation name is '_LC3_A23', type is buried 
_LC3_A23 = LCELL( _EQ002);
  _EQ002 =  A0 &  A1 &  A2 & !A3;

-- Node name is ':275' 
-- Equation name is '_LC4_A24', type is buried 
_LC4_A24 = LCELL( _EQ003);
  _EQ003 = !A0 &  A1 &  A2 & !A3;

-- Node name is ':280' 
-- Equation name is '_LC8_A19', type is buried 
_LC8_A19 = LCELL( _EQ004);
  _EQ004 = !_LC3_A23 &  _LC4_A19
         # !_LC3_A23 &  _LC4_A23;

-- Node name is ':299' 
-- Equation name is '_LC2_A23', type is buried 
!_LC2_A23 = _LC2_A23~NOT;
_LC2_A23~NOT = LCELL( _EQ005);
  _EQ005 =  A3
         # !A2
         #  A1
         #  A0;

-- Node name is ':311' 
-- Equation name is '_LC8_A23', type is buried 
_LC8_A23 = LCELL( _EQ006);
  _EQ006 =  A0 &  A1 & !A2 & !A3;

-- Node name is ':323' 
-- Equation name is '_LC6_A23', type is buried 
_LC6_A23 = LCELL( _EQ007);
  _EQ007 = !A0 &  A1 & !A2 & !A3;

-- Node name is '~326~1' 
-- Equation name is '~326~1', location is LC1_A23, type is buried.
-- synthesized logic cell 
_LC1_A23 = LCELL( _EQ008);
  _EQ008 =  A0 & !A1 &  A2 & !A3
         # !A0 &  A1 &  A2 & !A3;

-- Node name is ':335' 
-- Equation name is '_LC7_A23', type is buried 
!_LC7_A23 = _LC7_A23~NOT;
_LC7_A23~NOT = LCELL( _EQ009);
  _EQ009 =  A3
         #  A2
         #  A1
         # !A0;

-- Node name is ':347' 
-- Equation name is '_LC5_A23', type is buried 
_LC5_A23 = LCELL( _EQ010);
  _EQ010 = !A0 & !A1 & !A2 & !A3;

-- Node name is ':350' 
-- Equation name is '_LC4_A19', type is buried 
_LC4_A19 = LCELL( _EQ011);
  _EQ011 =  _LC5_A19 &  _LC8_A19
         #  _LC2_A19 &  _LC5_A19
         #  _LC2_A24 &  _LC5_A19;

-- Node name is '~352~1' 
-- Equation name is '~352~1', location is LC5_A19, type is buried.
-- synthesized logic cell 
!_LC5_A19 = _LC5_A19~NOT;
_LC5_A19~NOT = LCELL( _EQ012);
  _EQ012 =  _LC5_A23
         #  _LC7_A23;

-- Node name is ':367' 
-- Equation name is '_LC6_A19', type is buried 
_LC6_A19 = LCELL( _EQ013);
  _EQ013 =  _LC1_A19 & !_LC3_A23
         # !_LC3_A23 &  _LC4_A23;

-- Node name is ':383' 
-- Equation name is '_LC1_A19', type is buried 
_LC1_A19 = LCELL( _EQ014);
  _EQ014 =  _LC6_A19 &  _LC7_A19
         #  _LC2_A19 &  _LC7_A19
         #  _LC5_A23;

-- Node name is '~385~1' 
-- Equation name is '~385~1', location is LC7_A19, type is buried.
-- synthesized logic cell 
_LC7_A19 = LCELL( _EQ015);
  _EQ015 = !_LC2_A24 & !_LC7_A23;

-- Node name is ':400' 
-- Equation name is '_LC6_A24', type is buried 
_LC6_A24 = LCELL( _EQ016);
  _EQ016 = !A0 & !_LC3_A23 &  _LC4_A23
         # !_LC3_A23 & !_LC4_A23 &  _LC8_A24
         # !A0 & !_LC3_A23 &  _LC8_A24;

-- Node name is '~412~1' 
-- Equation name is '~412~1', location is LC5_A24, type is buried.
-- synthesized logic cell 
_LC5_A24 = LCELL( _EQ017);
  _EQ017 =  A3
         # !A0
         #  A1 &  A2
         # !A1 & !A2;

-- Node name is ':412' 
-- Equation name is '_LC7_A24', type is buried 
_LC7_A24 = LCELL( _EQ018);
  _EQ018 = !_LC2_A23 &  _LC4_A24 &  _LC5_A24
         # !_LC2_A23 &  _LC5_A24 &  _LC6_A24;

-- Node name is ':416' 
-- Equation name is '_LC8_A24', type is buried 
_LC8_A24 = LCELL( _EQ019);
  _EQ019 = !_LC7_A23 &  _LC7_A24
         #  _LC6_A23 & !_LC7_A23
         #  _LC5_A23;

-- Node name is ':433' 
-- Equation name is '_LC5_A22', type is buried 
_LC5_A22 = LCELL( _EQ020);
  _EQ020 = !_LC3_A23 &  _LC4_A22
         # !_LC3_A23 &  _LC4_A23;

-- Node name is ':442' 
-- Equation name is '_LC7_A22', type is buried 
_LC7_A22 = LCELL( _EQ021);
  _EQ021 = !_LC2_A23 &  _LC5_A22
         #  _LC1_A23 & !_LC2_A23;

-- Node name is ':449' 
-- Equation name is '_LC4_A22', type is buried 
_LC4_A22 = LCELL( _EQ022);
  _EQ022 =  _LC7_A22 & !_LC7_A23
         #  _LC2_A24 & !_LC7_A23
         #  _LC5_A23;

-- Node name is '~473~1' 
-- Equation name is '~473~1', location is LC1_A22, type is buried.
-- synthesized logic cell 
_LC1_A22 = LCELL( _EQ023);
  _EQ023 =  _LC3_A23
         #  _LC4_A23;

-- Node name is '~473~2' 
-- Equation name is '~473~2', location is LC2_A19, type is buried.
-- synthesized logic cell 
_LC2_A19 = LCELL( _EQ024);
  _EQ024 =  _LC2_A23
         #  _LC1_A23;

-- Node name is '~473~3' 
-- Equation name is '~473~3', location is LC1_A24, type is buried.
-- synthesized logic cell 
_LC1_A24 = LCELL( _EQ025);
  _EQ025 =  _LC2_A19
         #  _LC3_A24
         #  _LC3_A23
         #  _LC8_A23;

-- Node name is ':482' 
-- Equation name is '_LC3_A19', type is buried 
_LC3_A19 = LCELL( _EQ026);
  _EQ026 = !_LC5_A19
         #  _LC3_A19 & !_LC6_A23
         #  _LC1_A24 & !_LC6_A23;

-- Node name is '~494~1' 
-- Equation name is '~494~1', location is LC3_A24, type is buried.
-- synthesized logic cell 
_LC3_A24 = LCELL( _LC4_A23);

-- Node name is '~515~1' 
-- Equation name is '~515~1', location is LC3_A22, type is buried.
-- synthesized logic cell 
_LC3_A22 = LCELL( _EQ027);
  _EQ027 =  _LC7_A23
         #  _LC2_A24
         #  _LC2_A23
         #  _LC5_A23;

-- Node name is ':515' 
-- Equation name is '_LC8_A22', type is buried 
_LC8_A22 = LCELL( _EQ028);
  _EQ028 = !_LC1_A23 &  _LC8_A22
         #  _LC1_A22 & !_LC1_A23
         #  _LC3_A22;

-- Node name is ':541' 
-- Equation name is '_LC2_A22', type is buried 
_LC2_A22 = LCELL( _EQ029);
  _EQ029 = !_LC2_A23 &  _LC6_A22
         #  _LC1_A23 & !_LC2_A23
         #  _LC1_A22 & !_LC2_A23;

-- Node name is '~542~1' 
-- Equation name is '~542~1', location is LC2_A24, type is buried.
-- synthesized logic cell 
_LC2_A24 = LCELL( _EQ030);
  _EQ030 =  _LC6_A23
         #  _LC8_A23;

-- Node name is ':548' 
-- Equation name is '_LC6_A22', type is buried 
_LC6_A22 = LCELL( _EQ031);
  _EQ031 =  _LC5_A23
         #  _LC2_A24 & !_LC7_A23
         #  _LC2_A22 & !_LC7_A23;



Project Information                                         e:\vhdl\decl7s.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:03
   Timing SNF Extractor                   00:00:01
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:05


Memory Allocated
-----------------

Peak memory allocated during compilation  = 9,982K