decl7s.vhd

来自「7段数码显示译码器」· VHDL 代码 · 共 26 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY DECL7S IS
 PORT(A:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
  LED7S:OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END DECL7S;
ARCHITECTURE one OF DECL7S IS
BEGIN
 PROCESS(A)
 BEGIN
 CASE A IS
   WHEN"0000"=>LED7S<="0111111";
   WHEN"0001"=>LED7S<="0000110";
   WHEN"0010"=>LED7S<="1011011";
   WHEN"0011"=>LED7S<="1001111";
   WHEN"0100"=>LED7S<="1100110";
   WHEN"0101"=>LED7S<="1101101";
   WHEN"0110"=>LED7S<="1111101";
   WHEN"0111"=>LED7S<="0000111";
   WHEN"1000"=>LED7S<="1111111";
   WHEN"1001"=>LED7S<="1101111";
   WHEN OTHERS=>NULL;
 END CASE;
END PROCESS;
END one;