rom.rpt

用vhdl写的

-- Equation name is 'data2', location is LC013, type is output.
 data2   = LCELL( _EQ003 $  GND);
  _EQ003 =  address0 &  address1 &  address2 & !address4 & !address5 & 
             !address6 & !address7 & !cs
         # !address0 & !address1 &  address3 & !address4 & !address5 & 
             !address6 & !address7 & !cs
         #  cs &  _LC012;

-- Node name is 'data3' 
-- Equation name is 'data3', location is LC011, type is output.
 data3   = LCELL( _EQ004 $  GND);
  _EQ004 =  address0 &  address2 &  address3 & !address4 & !address5 & 
             !address6 & !address7 & !cs
         #  address0 &  address1 &  address2 & !address4 & !address5 & 
             !address6 & !address7 & !cs
         #  cs &  _LC008;

-- Node name is 'data4' 
-- Equation name is 'data4', location is LC032, type is output.
 data4   = LCELL( _EQ005 $  GND);
  _EQ005 = !address0 &  address1 & !address2 &  address3 & !address4 & 
             !address5 & !address6 & !address7 & !cs
         # !address0 &  address1 &  address2 & !address3 & !address4 & 
             !address5 & !address6 & !address7 & !cs
         #  address0 & !address1 &  address3 & !address4 & !address5 & 
             !address6 & !address7 & !cs
         #  address0 & !address2 & !address3 & !address4 & !address5 & 
             !address6 & !address7 & !cs
         #  cs &  _LC004;

-- Node name is 'data5' 
-- Equation name is 'data5', location is LC030, type is output.
 data5   = LCELL( _EQ006 $  GND);
  _EQ006 =  address0 &  address1 & !address2 &  address3 & !address4 & 
             !address5 & !address6 & !address7 & !cs
         #  address0 & !address1 &  address2 & !address4 & !address5 & 
             !address6 & !address7 & !cs
         # !address0 &  address1 &  address2 & !address4 & !address5 & 
             !address6 & !address7 & !cs
         #  cs &  _LC023;

-- Node name is 'data6' 
-- Equation name is 'data6', location is LC028, type is output.
 data6   = LCELL( _EQ007 $  GND);
  _EQ007 = !address0 &  address1 &  address3 & !address4 & !address5 & 
             !address6 & !address7 & !cs
         #  address0 & !address1 &  address3 & !address4 & !address5 & 
             !address6 & !address7 & !cs
         # !address2 &  address3 & !address4 & !address5 & !address6 & 
             !address7 & !cs
         #  cs &  _LC021;

-- Node name is 'data7' 
-- Equation name is 'data7', location is LC027, type is output.
 data7   = LCELL( _EQ008 $  GND);
  _EQ008 =  cs &  _LC019
         # !cs &  _LC026;

-- Node name is '~5902~1' 
-- Equation name is '~5902~1', location is LC026, type is buried.
-- synthesized logic cell 
_LC026   = LCELL( _EQ009 $  GND);
  _EQ009 = !address0 &  address1 &  address2 & !address4 & !address5 & 
             !address6 & !address7
         # !address2 &  address3 & !address4 & !address5 & !address6 & 
             !address7
         #  address0 & !address2 & !address4 & !address5 & !address6 & 
             !address7
         #  address0 & !address1 & !address4 & !address5 & !address6 & 
             !address7
         # !address1 & !address2 & !address4 & !address5 & !address6 & 
             !address7;

-- Node name is '~6259~1' 
-- Equation name is '~6259~1', location is LC017, type is buried.
-- synthesized logic cell 
_LC017   = LCELL( _EQ010 $  GND);
  _EQ010 = !address0 & !address1 &  address2 &  address3 & !address4 & 
             !address5 & !address6 & !address7
         #  address0 &  address1 &  address2 & !address4 & !address5 & 
             !address6 & !address7
         #  address0 &  address2 & !address3 & !address4 & !address5 & 
             !address6 & !address7
         # !address0 &  address1 & !address2 & !address4 & !address5 & 
             !address6 & !address7
         #  address0 & !address1 & !address2 & !address4 & !address5 & 
             !address6 & !address7;

-- Node name is '~6279~1~2' 
-- Equation name is '~6279~1~2', location is LC018, type is buried.
-- synthesized logic cell 
_LC018   = LCELL( _EQ011 $  GND);
  _EQ011 = !address0 &  address1 & !address4 & !address5 & !address6 & 
             !address7 & !cs &  _X001
         # !address0 &  address1 &  address2 & !address4 & !address5 & 
             !address6 & !address7 &  _LC019
         #  address0 & !address1 & !address4 & !address5 & !address6 & 
             !address7 &  _LC019
         # !address2 & !address4 & !address5 & !address6 & !address7 & 
              _LC019 &  _X001;
  _X001  = EXP(!address0 &  address1 & !address3);

-- Node name is '~6279~1' 
-- Equation name is '~6279~1', location is LC019, type is buried.
-- synthesized logic cell 
_LC019   = LCELL( _EQ012 $  GND);
  _EQ012 = !address0 &  address1 &  address2 & !address4 & !address5 & 
             !address6 & !address7 & !cs
         #  address0 & !address1 & !address4 & !address5 & !address6 & 
             !address7 & !cs
         # !address2 & !address4 & !address5 & !address6 & !address7 & !cs & 
              _X001
         #  cs &  _LC019
         #  _LC018;
  _X001  = EXP(!address0 &  address1 & !address3);

-- Node name is '~6285~1~2' 
-- Equation name is '~6285~1~2', location is LC020, type is buried.
-- synthesized logic cell 
_LC020   = LCELL( _EQ013 $  GND);
  _EQ013 = !address0 &  address1 &  address3 & !address4 & !address5 & 
             !address6 & !address7 &  _LC021
         #  address0 & !address1 &  address3 & !address4 & !address5 & 
             !address6 & !address7 &  _LC021
         # !address2 &  address3 & !address4 & !address5 & !address6 & 
             !address7 &  _LC021;

-- Node name is '~6285~1' 
-- Equation name is '~6285~1', location is LC021, type is buried.
-- synthesized logic cell 
_LC021   = LCELL( _EQ014 $  GND);
  _EQ014 = !address0 &  address1 &  address3 & !address4 & !address5 & 
             !address6 & !address7 & !cs
         #  address0 & !address1 &  address3 & !address4 & !address5 & 
             !address6 & !address7 & !cs
         # !address2 &  address3 & !address4 & !address5 & !address6 & 
             !address7 & !cs
         #  cs &  _LC021
         #  _LC020;

-- Node name is '~6291~1~2' 
-- Equation name is '~6291~1~2', location is LC022, type is buried.
-- synthesized logic cell 
_LC022   = LCELL( _EQ015 $  GND);
  _EQ015 =  address0 &  address1 & !address2 &  address3 & !address4 & 
             !address5 & !address6 & !address7 &  _LC023
         #  address0 & !address1 &  address2 & !address4 & !address5 & 
             !address6 & !address7 &  _LC023
         # !address0 &  address1 &  address2 & !address4 & !address5 & 
             !address6 & !address7 &  _LC023;

-- Node name is '~6291~1' 
-- Equation name is '~6291~1', location is LC023, type is buried.
-- synthesized logic cell 
_LC023   = LCELL( _EQ016 $  GND);
  _EQ016 =  address0 &  address1 & !address2 &  address3 & !address4 & 
             !address5 & !address6 & !address7 & !cs
         #  address0 & !address1 &  address2 & !address4 & !address5 & 
             !address6 & !address7 & !cs
         # !address0 &  address1 &  address2 & !address4 & !address5 & 
             !address6 & !address7 & !cs
         #  cs &  _LC023
         #  _LC022;

-- Node name is '~6297~1~2' 
-- Equation name is '~6297~1~2', location is LC024, type is buried.
-- synthesized logic cell 
_LC024   = LCELL( _EQ017 $  GND);
  _EQ017 = !address0 &  address1 & !address2 &  address3 & !address4 & 
             !address5 & !address6 & !address7 &  _LC004
         # !address0 &  address1 &  address2 & !address3 & !address4 & 
             !address5 & !address6 & !address7 &  _LC004
         #  address0 & !address1 & !address2 & !address4 & !address5 & 
             !address6 & !address7 & !cs
         #  address0 & !address1 &  address3 & !address4 & !address5 & 
             !address6 & !address7 &  _LC004
         #  address0 & !address2 & !address3 & !address4 & !address5 & 
             !address6 & !address7 &  _LC004;

-- Node name is '~6297~1~3' 
-- Equation name is '~6297~1~3', location is LC025, type is buried.
-- synthesized logic cell 
_LC025   = LCELL( _EQ018 $  GND);
  _EQ018 =  cs &  _LC004
         #  _LC024;

-- Node name is '~6297~1' 
-- Equation name is '~6297~1', location is LC004, type is buried.
-- synthesized logic cell 
_LC004   = LCELL( _EQ019 $  GND);
  _EQ019 = !address0 &  address1 & !address2 &  address3 & !address4 & 
             !address5 & !address6 & !address7 & !cs
         # !address0 &  address1 &  address2 & !address3 & !address4 & 
             !address5 & !address6 & !address7 & !cs
         #  address0 & !address1 &  address3 & !address4 & !address5 & 
             !address6 & !address7 & !cs
         #  address0 & !address2 & !address3 & !address4 & !address5 & 
             !address6 & !address7 & !cs
         #  _LC025;

-- Node name is '~6303~1' 
-- Equation name is '~6303~1', location is LC008, type is buried.
-- synthesized logic cell 
_LC008   = LCELL( _EQ020 $  GND);
  _EQ020 =  address0 &  address2 &  address3 & !address4 & !address5 & 
             !address6 & !address7 & !cs
         #  address0 &  address1 &  address2 & !address4 & !address5 & 
             !address6 & !address7 & !cs
         #  cs &  _LC008
         #  address0 &  address2 &  address3 & !address4 & !address5 & 
             !address6 & !address7 &  _LC008
         #  address0 &  address1 &  address2 & !address4 & !address5 & 
             !address6 & !address7 &  _LC008;

-- Node name is '~6309~1' 
-- Equation name is '~6309~1', location is LC012, type is buried.
-- synthesized logic cell 
_LC012   = LCELL( _EQ021 $  GND);
  _EQ021 =  address0 &  address1 &  address2 & !address4 & !address5 & 
             !address6 & !address7 & !cs
         # !address0 & !address1 &  address3 & !address4 & !address5 & 
             !address6 & !address7 & !cs
         #  cs &  _LC012
         #  address0 &  address1 &  address2 & !address4 & !address5 & 
             !address6 & !address7 &  _LC012
         # !address0 & !address1 &  address3 & !address4 & !address5 & 
             !address6 & !address7 &  _LC012;

-- Node name is '~6315~1' 
-- Equation name is '~6315~1', location is LC029, type is buried.
-- synthesized logic cell 
_LC029   = LCELL( _EQ022 $  GND);
  _EQ022 =  address0 &  address1 & !address2 & !address3 & !address4 & 
             !address5 & !address6 & !address7 & !cs
         # !address0 & !address1 & !address2 &  address3 & !address4 & 
             !address5 & !address6 & !address7 & !cs
         #  cs &  _LC029
         #  address0 &  address1 & !address2 & !address3 & !address4 & 
             !address5 & !address6 & !address7 &  _LC029
         # !address0 & !address1 & !address2 &  address3 & !address4 & 
             !address5 & !address6 & !address7 &  _LC029;

-- Node name is '~6321~1' 
-- Equation name is '~6321~1', location is LC016, type is buried.
-- synthesized logic cell 
_LC016   = LCELL( _EQ023 $  GND);
  _EQ023 =  cs &  _LC016
         # !cs &  _LC017
         #  _LC016 &  _LC017;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                        d:\xiaoning\rom.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 19,982K