📄 top.rpt
字号:
- 5 - A 02 DFFE 1 4 0 6 |LS273:7|:20
- 8 - A 14 DFFE 1 4 0 7 |LS273:7|:22
- 1 - B 11 DFFE 1 4 0 10 |LS273:7|:24
- 1 - A 10 DFFE 1 4 0 4 |LS273:8|:10
- 2 - B 01 DFFE 1 4 0 4 |LS273:8|:12
- 7 - A 10 DFFE 1 4 0 6 |LS273:8|:14
- 8 - A 23 DFFE 1 4 0 4 |LS273:8|:16
- 7 - A 22 DFFE 1 4 0 4 |LS273:8|:18
- 1 - B 06 DFFE 1 4 0 4 |LS273:8|:20
- 2 - A 14 DFFE 1 4 0 4 |LS273:8|:22
- 4 - B 01 DFFE 1 4 0 7 |LS273:8|:24
- 8 - A 08 DFFE 1 4 0 1 |LS273:10|:10
- 8 - B 09 DFFE 1 4 0 1 |LS273:10|:12
- 5 - B 08 DFFE 1 4 0 1 |LS273:10|:14
- 8 - A 02 DFFE 1 4 0 1 |LS273:10|:16
- 5 - B 20 DFFE 1 4 0 1 |LS273:10|:18
- 2 - A 02 DFFE 1 4 0 1 |LS273:10|:20
- 7 - B 18 DFFE 1 4 0 1 |LS273:10|:22
- 6 - B 18 DFFE 1 4 0 1 |LS273:10|:24
- 7 - A 08 DFFE 1 4 0 1 |LS273:11|:10
- 6 - B 09 DFFE 1 4 0 1 |LS273:11|:12
- 6 - B 04 DFFE 1 4 0 1 |LS273:11|:14
- 6 - A 17 DFFE 1 4 0 1 |LS273:11|:16
- 7 - A 24 DFFE 1 4 0 1 |LS273:11|:18
- 5 - B 04 DFFE 1 4 0 1 |LS273:11|:20
- 6 - A 19 DFFE 1 4 0 1 |LS273:11|:22
- 5 - B 18 DFFE 1 4 0 1 |LS273:11|:24
- 3 - A 10 DFFE 1 4 0 1 |LS273:12|:10
- 2 - B 10 DFFE 1 4 0 1 |LS273:12|:12
- 4 - B 04 DFFE 1 4 0 1 |LS273:12|:14
- 5 - A 17 DFFE 1 4 0 1 |LS273:12|:16
- 6 - A 24 DFFE 1 4 0 1 |LS273:12|:18
- 8 - B 03 DFFE 1 4 0 1 |LS273:12|:20
- 4 - A 19 DFFE 1 4 0 1 |LS273:12|:22
- 3 - B 11 DFFE 1 4 0 1 |LS273:12|:24
- 3 - B 02 DFFE 0 2 0 1 |LS273:14|:10
- 2 - B 02 DFFE 0 2 0 1 |LS273:14|:12
- 1 - B 02 DFFE 0 2 0 1 |LS273:14|:14
- 5 - B 02 DFFE 0 2 0 2 |LS273:14|:16
- 8 - B 12 DFFE 0 2 0 19 |LS273:14|:18
- 1 - B 07 DFFE 0 2 0 12 |LS273:14|:20
- 6 - B 12 DFFE 0 2 0 9 |LS273:14|:22
- 6 - B 02 DFFE 0 2 0 4 |LS273:14|:24
- 6 - A 07 DFFE 0 3 0 69 |MODE_CONTROL:26|M (|MODE_CONTROL:26|:37)
- 3 - A 04 OR2 s ! 0 2 0 1 |MODE_CONTROL:26|~121~1
- 6 - A 04 OR2 s 0 4 0 1 |MODE_CONTROL:26|~121~2
- 4 - A 04 AND2 0 4 0 2 |MODE_CONTROL:26|:858
- 2 - A 04 AND2 0 4 0 4 |MODE_CONTROL:26|:870
- 1 - A 04 AND2 0 4 0 2 |MODE_CONTROL:26|:894
- 2 - A 09 AND2 0 4 0 2 |MODE_CONTROL:26|:906
- 5 - A 04 AND2 0 4 0 3 |MODE_CONTROL:26|:918
- 1 - A 09 AND2 s 0 3 0 3 |MODE_CONTROL:26|~930~1
- 7 - A 04 AND2 0 4 0 2 |MODE_CONTROL:26|:935
- 4 - A 07 OR2 0 4 0 8 |MODE_CONTROL:26|:1137
- 5 - A 09 OR2 0 3 0 5 |MODE_CONTROL:26|:1141
- 2 - A 07 AND2 1 3 0 8 |MODE_CONTROL:26|:1149
- 6 - A 09 OR2 ! 0 4 0 2 |MODE_CONTROL:26|:1155
- 3 - A 07 OR2 ! 0 3 0 10 |MODE_CONTROL:26|:1161
- 3 - A 03 AND2 ! 0 2 0 4 |MODE_CONTROL:26|:1162
- 7 - A 05 OR2 ! 0 3 0 8 |MODE_CONTROL:26|:1182
- 8 - A 04 OR2 s 0 4 0 3 |MODE_CONTROL:26|~1233~1
- 6 - A 05 OR2 0 4 0 8 |MODE_CONTROL:26|:1233
- 3 - A 12 AND2 1 2 0 8 |MODE_CONTROL:26|:1241
- 1 - A 16 AND2 1 1 0 2 |MODE_CONTROL:26|:1250
- 7 - A 07 OR2 0 4 0 3 |MODE_CONTROL:26|:1261
- 1 - A 07 AND2 s ! 0 2 0 1 |MODE_CONTROL:26|~1283~1
- 5 - A 07 OR2 0 4 0 3 |MODE_CONTROL:26|:1283
- 4 - A 06 AND2 ! 0 3 0 1 |MODE_CONTROL:26|:1306
- 3 - A 06 OR2 ! 0 4 0 4 |MODE_CONTROL:26|:1328
- 1 - A 06 OR2 0 3 0 1 |MODE_CONTROL:26|:1351
- 8 - A 06 OR2 0 4 0 4 |MODE_CONTROL:26|:1374
- 5 - A 06 OR2 0 3 0 1 |MODE_CONTROL:26|:1397
- 2 - A 06 OR2 0 4 0 4 |MODE_CONTROL:26|:1420
- 7 - A 09 AND2 s 0 3 0 57 |MODE_CONTROL:26|~1430~1
- 3 - A 05 OR2 s 0 4 0 1 |MODE_CONTROL:26|~1459~1
- 4 - A 03 OR2 1 3 0 3 |MODE_CONTROL:26|:1459
- 8 - A 10 AND2 0 3 0 8 |MODE_CONTROL:26|:1483
- 5 - A 10 AND2 0 3 0 8 |MODE_CONTROL:26|:1506
- 4 - A 10 AND2 0 3 0 8 |MODE_CONTROL:26|:1529
- 4 - A 09 AND2 0 3 0 12 |MODE_CONTROL:26|:1542
- 8 - A 05 OR2 s ! 0 3 0 1 |MODE_CONTROL:26|~1573~1
- 7 - A 12 OR2 0 3 0 17 |MODE_CONTROL:26|:1573
- 4 - A 05 OR2 0 4 0 2 |MODE_CONTROL:26|:1595
- 1 - A 05 AND2 1 2 0 8 |MODE_CONTROL:26|:1601
- 2 - A 05 AND2 s 1 1 0 2 |MUX2:15|~44~1
- 8 - A 07 OR2 ! 1 3 0 16 |MUX2:15|:44
- 2 - B 14 OR2 0 2 0 1 |MUX2:15|:118
- 4 - B 09 OR2 0 2 0 1 |MUX2:15|:124
- 3 - B 08 OR2 0 2 0 1 |MUX2:15|:130
- 4 - A 02 OR2 0 2 0 1 |MUX2:15|:136
- 3 - B 20 OR2 0 2 0 1 |MUX2:15|:142
- 7 - B 03 OR2 0 2 0 1 |MUX2:15|:148
- 3 - B 15 OR2 0 2 0 1 |MUX2:15|:154
- 6 - B 24 OR2 0 2 0 1 |MUX2:15|:160
- 1 - A 08 OR2 0 2 1 0 |MUX2:15|:166
- 7 - B 09 OR2 0 2 1 0 |MUX2:15|:172
- 2 - B 08 OR2 0 2 1 0 |MUX2:15|:178
- 3 - A 02 OR2 0 2 1 0 |MUX2:15|:184
- 6 - B 20 OR2 0 2 1 0 |MUX2:15|:190
- 1 - B 03 OR2 0 2 1 0 |MUX2:15|:196
- 8 - B 18 OR2 0 2 1 0 |MUX2:15|:202
- 1 - B 18 OR2 0 2 1 0 |MUX2:15|:208
- 8 - A 03 AND2 0 4 0 8 |MUX4:29|:113
- 7 - A 03 OR2 ! 0 4 0 8 |MUX4:29|:122
- 1 - A 03 AND2 0 4 0 8 |MUX4:29|:131
- 2 - A 03 AND2 0 4 0 8 |MUX4:29|:140
- 5 - A 08 OR2 0 4 0 1 |MUX4:29|:304
- 6 - A 08 OR2 0 3 0 1 |MUX4:29|:310
- 4 - A 08 OR2 0 3 0 2 |MUX4:29|:316
- 1 - B 10 OR2 0 4 0 1 |MUX4:29|:325
- 2 - B 09 OR2 0 3 0 1 |MUX4:29|:328
- 3 - B 09 OR2 0 3 0 2 |MUX4:29|:331
- 3 - B 04 OR2 0 4 0 1 |MUX4:29|:340
- 2 - B 04 OR2 0 3 0 1 |MUX4:29|:343
- 1 - B 08 OR2 0 3 0 2 |MUX4:29|:346
- 3 - A 17 OR2 0 4 0 1 |MUX4:29|:355
- 4 - A 17 OR2 0 3 0 1 |MUX4:29|:358
- 1 - A 02 OR2 0 3 0 2 |MUX4:29|:361
- 4 - A 24 OR2 0 4 0 1 |MUX4:29|:370
- 5 - A 24 OR2 0 3 0 1 |MUX4:29|:373
- 2 - B 20 OR2 0 3 0 2 |MUX4:29|:376
- 3 - B 03 OR2 0 4 0 1 |MUX4:29|:385
- 5 - B 03 OR2 0 3 0 1 |MUX4:29|:388
- 6 - B 03 OR2 0 3 0 2 |MUX4:29|:391
- 3 - A 19 OR2 0 4 0 1 |MUX4:29|:400
- 7 - A 19 OR2 0 3 0 1 |MUX4:29|:403
- 2 - B 18 OR2 0 3 0 2 |MUX4:29|:406
- 2 - B 11 OR2 s 0 4 0 1 |MUX4:29|~421~1
- 6 - B 11 OR2 s 0 4 0 1 |MUX4:29|~421~2
- 4 - B 18 OR2 s 0 3 0 1 |MUX4:29|~421~3
- 3 - B 18 OR2 0 3 0 2 |MUX4:29|:421
- 3 - B 06 AND2 0 2 0 1 |PC:9|LPM_ADD_SUB:132|addcore:adder|:121
- 1 - B 12 AND2 0 3 0 1 |PC:9|LPM_ADD_SUB:132|addcore:adder|:125
- 3 - B 12 AND2 0 4 0 4 |PC:9|LPM_ADD_SUB:132|addcore:adder|:129
- 2 - B 05 AND2 0 2 0 1 |PC:9|LPM_ADD_SUB:132|addcore:adder|:133
- 6 - B 05 AND2 0 3 0 1 |PC:9|LPM_ADD_SUB:132|addcore:adder|:137
- 8 - B 05 AND2 0 4 0 1 |PC:9|LPM_ADD_SUB:132|addcore:adder|:141
- 5 - B 05 DFFE 0 4 0 1 |PC:9|qout7 (|PC:9|:20)
- 4 - B 05 DFFE 0 4 0 2 |PC:9|qout6 (|PC:9|:21)
- 3 - B 05 DFFE 0 4 0 3 |PC:9|qout5 (|PC:9|:22)
- 1 - B 05 DFFE 0 4 0 4 |PC:9|qout4 (|PC:9|:23)
- 5 - B 12 DFFE 0 4 0 2 |PC:9|qout3 (|PC:9|:24)
- 8 - B 06 DFFE 0 4 0 3 |PC:9|qout2 (|PC:9|:25)
- 4 - B 12 DFFE 0 4 0 4 |PC:9|qout1 (|PC:9|:26)
- 2 - B 12 DFFE 0 3 0 5 |PC:9|qout0 (|PC:9|:27)
- 7 - B 02 AND2 0 4 0 2 |ROM1:43|:5943
- 8 - B 02 AND2 s 0 2 0 3 |ROM1:43|~5963~1
- 1 - B 14 AND2 s 0 2 0 5 |ROM1:43|~5963~2
- 1 - B 17 AND2 s 0 2 0 4 |ROM1:43|~5963~3
- 4 - B 17 AND2 s 0 4 0 1 |ROM1:43|~5963~4
- 5 - B 21 AND2 0 4 0 3 |ROM1:43|:5983
- 4 - B 02 AND2 s ! 0 3 0 2 |ROM1:43|~6063~1
- 8 - B 21 OR2 ! 0 4 0 7 |ROM1:43|:6103
- 1 - B 16 AND2 s ! 0 2 0 1 |ROM1:43|~6106~1
- 2 - B 17 AND2 0 3 0 6 |ROM1:43|:6123
- 1 - B 21 OR2 ! 0 4 0 3 |ROM1:43|:6143
- 6 - B 16 OR2 0 4 0 2 |ROM1:43|:6148
- 6 - B 17 AND2 s ! 0 3 0 6 |ROM1:43|~6163~1
- 6 - B 14 AND2 s ! 0 2 0 6 |ROM1:43|~6183~1
- 3 - B 21 OR2 s 0 3 0 6 |ROM1:43|~6183~2
- 5 - B 17 AND2 s ! 0 2 0 1 |ROM1:43|~6203~1
- 7 - B 17 OR2 ! 0 3 0 4 |ROM1:43|:6203
- 3 - B 14 OR2 0 4 0 1 |ROM1:43|:6208
- 6 - B 21 AND2 s ! 0 3 0 3 |ROM1:43|~6223~1
- 6 - B 15 AND2 0 2 0 4 |ROM1:43|:6223
- 3 - B 24 AND2 0 2 0 4 |ROM1:43|:6243
- 4 - B 14 OR2 0 4 0 1 |ROM1:43|:6248
- 7 - B 21 AND2 s ! 0 3 0 4 |ROM1:43|~6263~1
- 5 - B 14 OR2 s 0 4 0 1 |ROM1:43|~6266~1
- 8 - B 17 OR2 s 0 4 0 1 |ROM1:43|~6338~1
- 2 - B 16 OR2 0 4 0 2 |ROM1:43|:6338
- 3 - B 16 OR2 0 4 0 1 |ROM1:43|:6359
- 4 - B 21 OR2 0 4 0 1 |ROM1:43|:6410
- 2 - B 19 AND2 s 0 2 0 1 |ROM1:43|~6412~1
- 2 - B 21 OR2 0 4 0 1 |ROM1:43|:6421
- 8 - B 15 OR2 0 4 0 1 |ROM1:43|:6425
- 8 - B 13 OR2 0 4 0 1 |ROM1:43|:6461
- 6 - B 13 OR2 s 0 3 0 1 |ROM1:43|~6463~1
- 7 - B 13 OR2 s 0 3 0 1 |ROM1:43|~6463~2
- 4 - B 13 OR2 0 4 0 1 |ROM1:43|:6515
- 4 - B 15 OR2 0 3 0 1 |ROM1:43|:6584
- 1 - B 13 OR2 0 4 0 2 |ROM1:43|:6613
- 3 - B 17 OR2 s 0 4 0 6 |ROM1:43|~6617~1
- 3 - B 13 OR2 0 4 0 1 |ROM1:43|:6623
- 5 - B 13 OR2 0 4 0 1 |ROM1:43|:6629
- 4 - B 24 OR2 0 4 0 1 |ROM1:43|:6641
- 7 - B 14 OR2 0 3 0 1 |ROM1:43|:6664
- 5 - B 09 OR2 0 3 0 1 |ROM1:43|:6670
- 8 - B 24 AND2 s 0 4 0 2 |ROM1:43|~6671~1
- 8 - B 16 AND2 s 0 2 0 3 |ROM1:43|~6671~2
- 7 - B 16 OR2 0 3 0 1 |ROM1:43|:6676
- 2 - B 24 OR2 s 0 3 0 2 |ROM1:43|~6677~1
- 1 - B 15 OR2 0 3 0 1 |ROM1:43|:6682
- 7 - B 24 OR2 s 0 3 0 4 |ROM1:43|~6683~1
- 4 - B 20 OR2 0 3 0 1 |ROM1:43|:6688
- 2 - B 03 OR2 0 3 0 1 |ROM1:43|:6694
- 2 - B 13 OR2 s 0 3 0 3 |ROM1:43|~6695~1
- 7 - B 15 OR2 0 3 0 1 |ROM1:43|:6700
- 5 - B 15 AND2 s 0 2 0 1 |ROM1:43|~6701~1
- 5 - B 24 OR2 0 3 0 1 |ROM1:43|:6706
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\xiaoning\top.rpt
top
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 77/ 96( 80%) 15/ 48( 31%) 14/ 48( 29%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
B: 73/ 96( 76%) 19/ 48( 39%) 3/ 48( 6%) 2/16( 12%) 6/16( 37%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
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