mux2.rpt

用vhdl写的

LC23 -> - - - - - - * - - - - - - * - | - * | <-- ~202~1
LC18 -> - - - - - * - - - - - - - - * | - * | <-- ~208~1

Pin
4    -> * * * * * * * * * * * * * * * | * * | <-- LED_B
5    -> * * * * * * * * * * * * * * * | * * | <-- WR
6    -> * - - - - * - - - - - - - - * | - * | <-- X0
14   -> - * - - - - * - - - - - - * - | - * | <-- X1
13   -> - - * - - - - * - - - - * - - | - * | <-- X2
12   -> - - - * - - - - * - - * - - - | - * | <-- X3
11   -> - - - - * - - - - * * - - - - | - * | <-- X4


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                              d:\xiaoning\mux2.rpt
mux2

** EQUATIONS **

LED_B    : INPUT;
WR       : INPUT;
X0       : INPUT;
X1       : INPUT;
X2       : INPUT;
X3       : INPUT;
X4       : INPUT;
X5       : INPUT;
X6       : INPUT;
X7       : INPUT;

-- Node name is 'W10' = '~160~1' 
-- Equation name is 'W10', location is LC019, type is output.
 W10     = LCELL( _EQ001 $  X0);
  _EQ001 = !LED_B & !WR &  W10 & !X0
         # !LED_B & !WR & !W10 &  X0;

-- Node name is 'W11' = '~154~1' 
-- Equation name is 'W11', location is LC021, type is output.
 W11     = LCELL( _EQ002 $  X1);
  _EQ002 = !LED_B & !WR &  W11 & !X1
         # !LED_B & !WR & !W11 &  X1;

-- Node name is 'W12' = '~148~1' 
-- Equation name is 'W12', location is LC022, type is output.
 W12     = LCELL( _EQ003 $  X2);
  _EQ003 = !LED_B & !WR &  W12 & !X2
         # !LED_B & !WR & !W12 &  X2;

-- Node name is 'W13' = '~142~1' 
-- Equation name is 'W13', location is LC020, type is output.
 W13     = LCELL( _EQ004 $  X3);
  _EQ004 = !LED_B & !WR &  W13 & !X3
         # !LED_B & !WR & !W13 &  X3;

-- Node name is 'W14' = '~136~1' 
-- Equation name is 'W14', location is LC017, type is output.
 W14     = LCELL( _EQ005 $  X4);
  _EQ005 = !LED_B & !WR &  W14 & !X4
         # !LED_B & !WR & !W14 &  X4;

-- Node name is 'W15' = '~130~1' 
-- Equation name is 'W15', location is LC012, type is output.
 W15     = LCELL( _EQ006 $  X5);
  _EQ006 = !LED_B & !WR &  W15 & !X5
         # !LED_B & !WR & !W15 &  X5;

-- Node name is 'W16' = '~124~1' 
-- Equation name is 'W16', location is LC016, type is output.
 W16     = LCELL( _EQ007 $  X6);
  _EQ007 = !LED_B & !WR &  W16 & !X6
         # !LED_B & !WR & !W16 &  X6;

-- Node name is 'W17' = '~118~1' 
-- Equation name is 'W17', location is LC011, type is output.
 W17     = LCELL( _EQ008 $  X7);
  _EQ008 = !LED_B & !WR &  W17 & !X7
         # !LED_B & !WR & !W17 &  X7;

-- Node name is 'W20' 
-- Equation name is 'W20', location is LC031, type is output.
 W20     = LCELL( _EQ009 $  GND);
  _EQ009 = !LED_B & !WR &  X0
         #  _LC018 &  _X001;
  _X001  = EXP(!LED_B & !WR);

-- Node name is 'W21' 
-- Equation name is 'W21', location is LC026, type is output.
 W21     = LCELL( _EQ010 $  GND);
  _EQ010 = !LED_B & !WR &  X1
         #  _LC023 &  _X001;
  _X001  = EXP(!LED_B & !WR);

-- Node name is 'W22' 
-- Equation name is 'W22', location is LC027, type is output.
 W22     = LCELL( _EQ011 $  GND);
  _EQ011 = !LED_B & !WR &  X2
         #  _LC024 &  _X001;
  _X001  = EXP(!LED_B & !WR);

-- Node name is 'W23' 
-- Equation name is 'W23', location is LC028, type is output.
 W23     = LCELL( _EQ012 $  GND);
  _EQ012 = !LED_B & !WR &  X3
         #  _LC025 &  _X001;
  _X001  = EXP(!LED_B & !WR);

-- Node name is 'W24' 
-- Equation name is 'W24', location is LC030, type is output.
 W24     = LCELL( _EQ013 $  GND);
  _EQ013 = !LED_B & !WR &  X4
         #  _LC029 &  _X001;
  _X001  = EXP(!LED_B & !WR);

-- Node name is 'W25' 
-- Equation name is 'W25', location is LC015, type is output.
 W25     = LCELL( _EQ014 $  GND);
  _EQ014 = !LED_B & !WR &  X5
         #  _LC004 &  _X001;
  _X001  = EXP(!LED_B & !WR);

-- Node name is 'W26' 
-- Equation name is 'W26', location is LC014, type is output.
 W26     = LCELL( _EQ015 $  GND);
  _EQ015 = !LED_B & !WR &  X6
         #  _LC001 &  _X001;
  _X001  = EXP(!LED_B & !WR);

-- Node name is 'W27' 
-- Equation name is 'W27', location is LC013, type is output.
 W27     = LCELL( _EQ016 $  GND);
  _EQ016 = !LED_B & !WR &  X7
         #  _LC008 &  _X001;
  _X001  = EXP(!LED_B & !WR);

-- Node name is '~166~1' 
-- Equation name is '~166~1', location is LC008, type is buried.
-- synthesized logic cell 
_LC008   = LCELL( _EQ017 $  _LC008);
  _EQ017 = !_LC008 & !LED_B & !WR &  X7
         #  _LC008 & !LED_B & !WR & !X7;

-- Node name is '~172~1' 
-- Equation name is '~172~1', location is LC001, type is buried.
-- synthesized logic cell 
_LC001   = LCELL( _EQ018 $  GND);
  _EQ018 = !LED_B & !WR &  X6
         #  _LC001 &  _X001;
  _X001  = EXP(!LED_B & !WR);

-- Node name is '~178~1' 
-- Equation name is '~178~1', location is LC004, type is buried.
-- synthesized logic cell 
_LC004   = LCELL( _EQ019 $  GND);
  _EQ019 = !LED_B & !WR &  X5
         #  _LC004 &  _X001;
  _X001  = EXP(!LED_B & !WR);

-- Node name is '~184~1' 
-- Equation name is '~184~1', location is LC029, type is buried.
-- synthesized logic cell 
_LC029   = LCELL( _EQ020 $  GND);
  _EQ020 = !LED_B & !WR &  X4
         #  _LC029 &  _X001;
  _X001  = EXP(!LED_B & !WR);

-- Node name is '~190~1' 
-- Equation name is '~190~1', location is LC025, type is buried.
-- synthesized logic cell 
_LC025   = LCELL( _EQ021 $  GND);
  _EQ021 = !LED_B & !WR &  X3
         #  _LC025 &  _X001;
  _X001  = EXP(!LED_B & !WR);

-- Node name is '~196~1' 
-- Equation name is '~196~1', location is LC024, type is buried.
-- synthesized logic cell 
_LC024   = LCELL( _EQ022 $  GND);
  _EQ022 = !LED_B & !WR &  X2
         #  _LC024 &  _X001;
  _X001  = EXP(!LED_B & !WR);

-- Node name is '~202~1' 
-- Equation name is '~202~1', location is LC023, type is buried.
-- synthesized logic cell 
_LC023   = LCELL( _EQ023 $  GND);
  _EQ023 = !LED_B & !WR &  X1
         #  _LC023 &  _X001;
  _X001  = EXP(!LED_B & !WR);

-- Node name is '~208~1' 
-- Equation name is '~208~1', location is LC018, type is buried.
-- synthesized logic cell 
_LC018   = LCELL( _EQ024 $  GND);
  _EQ024 = !LED_B & !WR &  X0
         #  _LC018 &  _X001;
  _X001  = EXP(!LED_B & !WR);



--     Shareable expanders that are duplicated in multiple LABs:
--    _X001 occurs in LABs A, B




Project Information                                       d:\xiaoning\mux2.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:00


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,528K