📄 mux2.rpt
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Project Information d:\xiaoning\mux2.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 12/01/2004 19:34:15
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
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limited to modification, reverse engineering, de-compiling, or use with
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the intellectual property, including patents, copyrights, trademarks,
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***** Project compilation was successful
MUX2
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
mux2 EPM7032LC44-6 10 16 0 24 2 75 %
User Pins: 10 16 0
Device-Specific Information: d:\xiaoning\mux2.rpt
mux2
***** Logic for device 'mux2' compiled without errors.
Device: EPM7032LC44-6
Device Options:
Turbo Bit = ON
Security Bit = OFF
R
E
S
L E
E R
D V G G G G G W V
X W _ C N N N N N 1 E
0 R B C D D D D D 4 D
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
X7 | 7 39 | W10
X6 | 8 38 | W13
X5 | 9 37 | W11
GND | 10 36 | W12
X4 | 11 35 | VCC
X3 | 12 EPM7032LC44-6 34 | RESERVED
X2 | 13 33 | RESERVED
X1 | 14 32 | RESERVED
VCC | 15 31 | W21
W17 | 16 30 | GND
W15 | 17 29 | W22
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
W W W W G V R W W R W
2 2 2 1 N C E 2 2 E 2
7 6 5 6 D C S 0 4 S 3
E E
R R
V V
E E
D D
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: d:\xiaoning\mux2.rpt
mux2
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 9/16( 56%) 16/16(100%) 1/16( 6%) 11/36( 30%)
B: LC17 - LC32 15/16( 93%) 10/16( 62%) 1/16( 6%) 17/36( 47%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 26/32 ( 81%)
Total logic cells used: 24/32 ( 75%)
Total shareable expanders used: 2/32 ( 6%)
Total Turbo logic cells used: 24/32 ( 75%)
Total shareable expanders not available (n/a): 0/32 ( 0%)
Average fan-in: 4.00
Total fan-in: 96
Total input pins required: 10
Total output pins required: 16
Total bidirectional pins required: 0
Total logic cells required: 24
Total flipflops required: 0
Total product terms required: 59
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 1
Synthesized logic cells: 16/ 32 ( 50%)
Device-Specific Information: d:\xiaoning\mux2.rpt
mux2
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
4 (1) (A) INPUT 0 0 0 0 0 16 8 LED_B
5 (2) (A) INPUT 0 0 0 0 0 16 8 WR
6 (3) (A) INPUT 0 0 0 0 0 2 1 X0
14 (10) (A) INPUT 0 0 0 0 0 2 1 X1
13 (9) (A) INPUT 0 0 0 0 0 2 1 X2
12 (8) (A) INPUT 0 0 0 0 0 2 1 X3
11 (7) (A) INPUT 0 0 0 0 0 2 1 X4
9 (6) (A) INPUT 0 0 0 0 0 2 1 X5
8 (5) (A) INPUT 0 0 0 0 0 2 1 X6
7 (4) (A) INPUT 0 0 0 0 0 2 1 X7
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\xiaoning\mux2.rpt
mux2
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
39 19 B OUTPUT s t 0 0 0 3 1 1 0 W10
37 21 B OUTPUT s t 0 0 0 3 1 1 0 W11
36 22 B OUTPUT s t 0 0 0 3 1 1 0 W12
38 20 B OUTPUT s t 0 0 0 3 1 1 0 W13
41 17 B OUTPUT s t 0 0 0 3 1 1 0 W14
17 12 A OUTPUT s t 0 0 0 3 1 1 0 W15
21 16 A OUTPUT s t 0 0 0 3 1 1 0 W16
16 11 A OUTPUT s t 0 0 0 3 1 1 0 W17
25 31 B OUTPUT t 1 1 0 3 1 0 0 W20
31 26 B OUTPUT t 1 1 0 3 1 0 0 W21
29 27 B OUTPUT t 1 1 0 3 1 0 0 W22
28 28 B OUTPUT t 1 1 0 3 1 0 0 W23
26 30 B OUTPUT t 1 1 0 3 1 0 0 W24
20 15 A OUTPUT t 1 1 0 3 1 0 0 W25
19 14 A OUTPUT t 1 1 0 3 1 0 0 W26
18 13 A OUTPUT t 1 1 0 3 1 0 0 W27
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\xiaoning\mux2.rpt
mux2
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(12) 8 A LCELL s t 0 0 0 3 1 1 1 ~166~1
(4) 1 A LCELL s t 1 1 0 3 1 1 1 ~172~1
(7) 4 A LCELL s t 1 1 0 3 1 1 1 ~178~1
(27) 29 B LCELL s t 1 1 0 3 1 1 1 ~184~1
(32) 25 B LCELL s t 1 1 0 3 1 1 1 ~190~1
(33) 24 B LCELL s t 1 1 0 3 1 1 1 ~196~1
(34) 23 B LCELL s t 1 1 0 3 1 1 1 ~202~1
(40) 18 B LCELL s t 1 1 0 3 1 1 1 ~208~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\xiaoning\mux2.rpt
mux2
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+----------------- LC12 W15
| +--------------- LC16 W16
| | +------------- LC11 W17
| | | +----------- LC15 W25
| | | | +--------- LC14 W26
| | | | | +------- LC13 W27
| | | | | | +----- LC8 ~166~1
| | | | | | | +--- LC1 ~172~1
| | | | | | | | +- LC4 ~178~1
| | | | | | | | |
| | | | | | | | | Other LABs fed by signals
| | | | | | | | | that feed LAB 'A'
LC | | | | | | | | | | A B | Logic cells that feed LAB 'A':
LC12 -> * - - - - - - - - | * - | <-- W15
LC16 -> - * - - - - - - - | * - | <-- W16
LC11 -> - - * - - - - - - | * - | <-- W17
LC8 -> - - - - - * * - - | * - | <-- ~166~1
LC1 -> - - - - * - - * - | * - | <-- ~172~1
LC4 -> - - - * - - - - * | * - | <-- ~178~1
Pin
4 -> * * * * * * * * * | * * | <-- LED_B
5 -> * * * * * * * * * | * * | <-- WR
9 -> * - - * - - - - * | * - | <-- X5
8 -> - * - - * - - * - | * - | <-- X6
7 -> - - * - - * * - - | * - | <-- X7
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\xiaoning\mux2.rpt
mux2
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+----------------------------- LC19 W10
| +--------------------------- LC21 W11
| | +------------------------- LC22 W12
| | | +----------------------- LC20 W13
| | | | +--------------------- LC17 W14
| | | | | +------------------- LC31 W20
| | | | | | +----------------- LC26 W21
| | | | | | | +--------------- LC27 W22
| | | | | | | | +------------- LC28 W23
| | | | | | | | | +----------- LC30 W24
| | | | | | | | | | +--------- LC29 ~184~1
| | | | | | | | | | | +------- LC25 ~190~1
| | | | | | | | | | | | +----- LC24 ~196~1
| | | | | | | | | | | | | +--- LC23 ~202~1
| | | | | | | | | | | | | | +- LC18 ~208~1
| | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC19 -> * - - - - - - - - - - - - - - | - * | <-- W10
LC21 -> - * - - - - - - - - - - - - - | - * | <-- W11
LC22 -> - - * - - - - - - - - - - - - | - * | <-- W12
LC20 -> - - - * - - - - - - - - - - - | - * | <-- W13
LC17 -> - - - - * - - - - - - - - - - | - * | <-- W14
LC29 -> - - - - - - - - - * * - - - - | - * | <-- ~184~1
LC25 -> - - - - - - - - * - - * - - - | - * | <-- ~190~1
LC24 -> - - - - - - - * - - - - * - - | - * | <-- ~196~1
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