mux3.rpt

用vhdl写的

        | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | A B |     Logic cells that feed LAB 'B':

Pin
4    -> * * * * * * * * | - * | <-- cs
21   -> * - - - - - - - | - * | <-- in10
43   -> - * - - - - - - | - * | <-- in11
44   -> - - * - - - - - | - * | <-- in12
37   -> - - - * - - - - | - * | <-- in13
36   -> - - - - * - - - | - * | <-- in14
32   -> - - - - - * - - | - * | <-- in15
29   -> - - - - - - * - | - * | <-- in16
27   -> - - - - - - - * | - * | <-- in17
25   -> * - - - - - - - | - * | <-- in20
39   -> - * - - - - - - | - * | <-- in21
38   -> - - * - - - - - | - * | <-- in22
20   -> - - - * - - - - | - * | <-- in23
19   -> - - - - * - - - | - * | <-- in24
18   -> - - - - - * - - | - * | <-- in25
5    -> - - - - - - * - | - * | <-- in26
6    -> - - - - - - - * | - * | <-- in27
7    -> * - - - - - - - | - * | <-- in30
8    -> - * - - - - - - | - * | <-- in31
9    -> - - * - - - - - | - * | <-- in32
11   -> - - - * - - - - | - * | <-- in33
12   -> - - - - * - - - | - * | <-- in34
13   -> - - - - - * - - | - * | <-- in35
14   -> - - - - - - * - | - * | <-- in36
16   -> - - - - - - - * | - * | <-- in37
17   -> * * * * * * * * | - * | <-- sw_b


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                              d:\xiaoning\mux3.rpt
mux3

** EQUATIONS **

cs       : INPUT;
in10     : INPUT;
in11     : INPUT;
in12     : INPUT;
in13     : INPUT;
in14     : INPUT;
in15     : INPUT;
in16     : INPUT;
in17     : INPUT;
in20     : INPUT;
in21     : INPUT;
in22     : INPUT;
in23     : INPUT;
in24     : INPUT;
in25     : INPUT;
in26     : INPUT;
in27     : INPUT;
in30     : INPUT;
in31     : INPUT;
in32     : INPUT;
in33     : INPUT;
in34     : INPUT;
in35     : INPUT;
in36     : INPUT;
in37     : INPUT;
sw_b     : INPUT;

-- Node name is 'W0' 
-- Equation name is 'W0', location is LC030, type is output.
 W0      = LCELL( _EQ001 $  GND);
  _EQ001 =  cs &  in10 &  sw_b
         # !cs &  in30 &  sw_b
         #  in20 & !sw_b;

-- Node name is 'W1' 
-- Equation name is 'W1', location is LC018, type is output.
 W1      = LCELL( _EQ002 $  GND);
  _EQ002 =  cs &  in11 &  sw_b
         # !cs &  in31 &  sw_b
         #  in21 & !sw_b;

-- Node name is 'W2' 
-- Equation name is 'W2', location is LC017, type is output.
 W2      = LCELL( _EQ003 $  GND);
  _EQ003 =  cs &  in12 &  sw_b
         # !cs &  in32 &  sw_b
         #  in22 & !sw_b;

-- Node name is 'W3' 
-- Equation name is 'W3', location is LC032, type is output.
 W3      = LCELL( _EQ004 $  GND);
  _EQ004 =  cs &  in13 &  sw_b
         # !cs &  in33 &  sw_b
         #  in23 & !sw_b;

-- Node name is 'W4' 
-- Equation name is 'W4', location is LC023, type is output.
 W4      = LCELL( _EQ005 $  GND);
  _EQ005 =  cs &  in14 &  sw_b
         # !cs &  in34 &  sw_b
         #  in24 & !sw_b;

-- Node name is 'W5' 
-- Equation name is 'W5', location is LC024, type is output.
 W5      = LCELL( _EQ006 $  GND);
  _EQ006 =  cs &  in15 &  sw_b
         # !cs &  in35 &  sw_b
         #  in25 & !sw_b;

-- Node name is 'W6' 
-- Equation name is 'W6', location is LC026, type is output.
 W6      = LCELL( _EQ007 $  GND);
  _EQ007 =  cs &  in16 &  sw_b
         # !cs &  in36 &  sw_b
         #  in26 & !sw_b;

-- Node name is 'W7' 
-- Equation name is 'W7', location is LC028, type is output.
 W7      = LCELL( _EQ008 $  GND);
  _EQ008 =  cs &  in17 &  sw_b
         # !cs &  in37 &  sw_b
         #  in27 & !sw_b;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                       d:\xiaoning\mux3.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,416K