📄 mux3.rpt
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Project Information d:\xiaoning\mux3.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 12/01/2004 11:32:14
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
MUX3
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
mux3 EPM7032LC44-6 26 8 0 8 0 25 %
User Pins: 26 8 0
Device-Specific Information: d:\xiaoning\mux3.rpt
mux3
***** Logic for device 'mux3' compiled without errors.
Device: EPM7032LC44-6
Device Options:
Turbo Bit = ON
Security Bit = OFF
Device-Specific Information: d:\xiaoning\mux3.rpt
mux3
** ERROR SUMMARY **
Info: Chip 'mux3' in device 'EPM7032LC44-6' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
i i i i
n n V G G n n G
2 2 c C N N 1 1 N W W
7 6 s C D D 2 1 D 2 1
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
in30 | 7 39 | in21
in31 | 8 38 | in22
in32 | 9 37 | in13
GND | 10 36 | in14
in33 | 11 35 | VCC
in34 | 12 EPM7032LC44-6 34 | W4
in35 | 13 33 | W5
in36 | 14 32 | in15
VCC | 15 31 | W6
in37 | 16 30 | GND
sw_b | 17 29 | in16
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
i i i i G V W i W i W
n n n n N C 3 n 0 n 7
2 2 2 1 D C 2 1
5 4 3 0 0 7
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: d:\xiaoning\mux3.rpt
mux3
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 16/16(100%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 8/16( 50%) 16/16(100%) 0/16( 0%) 26/36( 72%)
Total dedicated input pins used: 2/4 ( 50%)
Total I/O pins used: 32/32 (100%)
Total logic cells used: 8/32 ( 25%)
Total shareable expanders used: 0/32 ( 0%)
Total Turbo logic cells used: 8/32 ( 25%)
Total shareable expanders not available (n/a): 0/32 ( 0%)
Average fan-in: 5.00
Total fan-in: 40
Total input pins required: 26
Total output pins required: 8
Total bidirectional pins required: 0
Total logic cells required: 8
Total flipflops required: 0
Total product terms required: 24
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 0
Synthesized logic cells: 0/ 32 ( 0%)
Device-Specific Information: d:\xiaoning\mux3.rpt
mux3
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
4 (1) (A) INPUT 0 0 0 0 0 8 0 cs
21 (16) (A) INPUT 0 0 0 0 0 1 0 in10
43 - - INPUT 0 0 0 0 0 1 0 in11
44 - - INPUT 0 0 0 0 0 1 0 in12
37 (21) (B) INPUT 0 0 0 0 0 1 0 in13
36 (22) (B) INPUT 0 0 0 0 0 1 0 in14
32 (25) (B) INPUT 0 0 0 0 0 1 0 in15
29 (27) (B) INPUT 0 0 0 0 0 1 0 in16
27 (29) (B) INPUT 0 0 0 0 0 1 0 in17
25 (31) (B) INPUT 0 0 0 0 0 1 0 in20
39 (19) (B) INPUT 0 0 0 0 0 1 0 in21
38 (20) (B) INPUT 0 0 0 0 0 1 0 in22
20 (15) (A) INPUT 0 0 0 0 0 1 0 in23
19 (14) (A) INPUT 0 0 0 0 0 1 0 in24
18 (13) (A) INPUT 0 0 0 0 0 1 0 in25
5 (2) (A) INPUT 0 0 0 0 0 1 0 in26
6 (3) (A) INPUT 0 0 0 0 0 1 0 in27
7 (4) (A) INPUT 0 0 0 0 0 1 0 in30
8 (5) (A) INPUT 0 0 0 0 0 1 0 in31
9 (6) (A) INPUT 0 0 0 0 0 1 0 in32
11 (7) (A) INPUT 0 0 0 0 0 1 0 in33
12 (8) (A) INPUT 0 0 0 0 0 1 0 in34
13 (9) (A) INPUT 0 0 0 0 0 1 0 in35
14 (10) (A) INPUT 0 0 0 0 0 1 0 in36
16 (11) (A) INPUT 0 0 0 0 0 1 0 in37
17 (12) (A) INPUT 0 0 0 0 0 8 0 sw_b
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\xiaoning\mux3.rpt
mux3
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
26 30 B OUTPUT t 0 0 0 5 0 0 0 W0
40 18 B OUTPUT t 0 0 0 5 0 0 0 W1
41 17 B OUTPUT t 0 0 0 5 0 0 0 W2
24 32 B OUTPUT t 0 0 0 5 0 0 0 W3
34 23 B OUTPUT t 0 0 0 5 0 0 0 W4
33 24 B OUTPUT t 0 0 0 5 0 0 0 W5
31 26 B OUTPUT t 0 0 0 5 0 0 0 W6
28 28 B OUTPUT t 0 0 0 5 0 0 0 W7
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\xiaoning\mux3.rpt
mux3
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+--------------- LC30 W0
| +------------- LC18 W1
| | +----------- LC17 W2
| | | +--------- LC32 W3
| | | | +------- LC23 W4
| | | | | +----- LC24 W5
| | | | | | +--- LC26 W6
| | | | | | | +- LC28 W7
| | | | | | | |
| | | | | | | | Other LABs fed by signals
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