rom1.rpt

用vhdl写的

-- Equation name is '~6338~1', location is LC7_B23, type is buried.
-- synthesized logic cell 
_LC7_B23 = LCELL( _EQ025);
  _EQ025 =  address2 &  address3 &  _LC5_B15
         #  _LC5_B18;

-- Node name is ':6338' 
-- Equation name is '_LC4_B23', type is buried 
_LC4_B23 = LCELL( _EQ026);
  _EQ026 = !_LC4_B15 &  _LC7_B23
         # !address3 &  _LC7_B23
         #  address3 & !_LC6_B18;

-- Node name is ':6359' 
-- Equation name is '_LC8_B23', type is buried 
_LC8_B23 = LCELL( _EQ027);
  _EQ027 = !_LC3_B23 &  _LC4_B23 & !_LC6_B23
         # !_LC5_B23;

-- Node name is ':6410' 
-- Equation name is '_LC4_B24', type is buried 
_LC4_B24 = LCELL( _EQ028);
  _EQ028 =  _LC3_B24 &  _LC5_B18
         #  _LC2_B15 &  _LC3_B24
         #  _LC2_B18;

-- Node name is '~6412~1' 
-- Equation name is '~6412~1', location is LC3_B24, type is buried.
-- synthesized logic cell 
_LC3_B24 = LCELL( _EQ029);
  _EQ029 = !_LC3_B23 & !_LC8_B18;

-- Node name is ':6421' 
-- Equation name is '_LC5_B24', type is buried 
_LC5_B24 = LCELL( _EQ030);
  _EQ030 =  address3 &  _LC4_B24
         # !_LC4_B15 &  _LC4_B24 &  _LC6_B18;

-- Node name is ':6425' 
-- Equation name is '_LC8_B24', type is buried 
_LC8_B24 = LCELL( _EQ031);
  _EQ031 = !_LC2_B23 &  _LC5_B24
         # !_LC2_B23 &  _LC3_B15
         #  _LC1_B15;

-- Node name is ':6461' 
-- Equation name is '_LC8_B20', type is buried 
_LC8_B20 = LCELL( _EQ032);
  _EQ032 = !_LC2_B15 &  _LC7_B20 & !_LC8_B18
         #  _LC3_B23;

-- Node name is '~6463~1' 
-- Equation name is '~6463~1', location is LC6_B20, type is buried.
-- synthesized logic cell 
_LC6_B20 = LCELL( _EQ033);
  _EQ033 = !address3
         # !_LC4_B15 &  _LC6_B18;

-- Node name is '~6463~2' 
-- Equation name is '~6463~2', location is LC7_B20, type is buried.
-- synthesized logic cell 
_LC7_B20 = LCELL( _EQ034);
  _EQ034 =  _LC5_B18 &  _LC6_B20
         #  _LC3_B16 &  _LC6_B20;

-- Node name is ':6515' 
-- Equation name is '_LC2_B21', type is buried 
_LC2_B21 = LCELL( _EQ035);
  _EQ035 =  _LC3_B23
         #  _LC8_B18
         # !_LC2_B15 &  _LC4_B21;

-- Node name is ':6584' 
-- Equation name is '_LC1_B24', type is buried 
_LC1_B24 = LCELL( _EQ036);
  _EQ036 =  _LC3_B15
         #  _LC2_B23
         #  _LC8_B18;

-- Node name is ':6613' 
-- Equation name is '_LC4_B21', type is buried 
_LC4_B21 = LCELL( _EQ037);
  _EQ037 =  _LC3_B16 &  _LC6_B18
         # !address3 &  _LC3_B16
         #  address3 &  _LC4_B15 &  _LC6_B18;

-- Node name is '~6617~1' 
-- Equation name is '~6617~1', location is LC2_B15, type is buried.
-- synthesized logic cell 
_LC2_B15 = LCELL( _EQ038);
  _EQ038 =  _LC6_B15
         #  address3 &  _LC7_B15
         #  address3 & !_LC3_B18;

-- Node name is ':6623' 
-- Equation name is '_LC5_B21', type is buried 
_LC5_B21 = LCELL( _EQ039);
  _EQ039 =  _LC3_B23
         #  _LC2_B15 & !_LC8_B18
         #  _LC4_B21 & !_LC8_B18;

-- Node name is ':6629' 
-- Equation name is '_LC6_B21', type is buried 
_LC6_B21 = LCELL( _EQ040);
  _EQ040 = !address3 &  _LC4_B15
         # !_LC2_B18 &  _LC5_B21;

-- Node name is ':6641' 
-- Equation name is '_LC8_B21', type is buried 
_LC8_B21 = LCELL( _EQ041);
  _EQ041 =  _LC6_B21 &  _LC7_B21
         #  _LC2_B23
         #  _LC1_B15;

-- Node name is ':6664' 
-- Equation name is '_LC8_B16', type is buried 
_LC8_B16 = LCELL( _EQ042);
  _EQ042 =  cs &  _LC8_B16
         # !cs &  _LC6_B16
         # !cs &  _LC7_B16;

-- Node name is ':6670' 
-- Equation name is '_LC4_B20', type is buried 
_LC4_B20 = LCELL( _EQ043);
  _EQ043 =  cs &  _LC4_B20
         #  _LC3_B20 &  _LC5_B20;

-- Node name is '~6671~1' 
-- Equation name is '~6671~1', location is LC1_B21, type is buried.
-- synthesized logic cell 
_LC1_B21 = LCELL( _EQ044);
  _EQ044 = !_LC1_B15 &  _LC1_B18 & !_LC2_B23 &  _LC7_B21;

-- Node name is '~6671~2' 
-- Equation name is '~6671~2', location is LC5_B20, type is buried.
-- synthesized logic cell 
_LC5_B20 = LCELL( _EQ045);
  _EQ045 =  _LC1_B21 &  _LC5_B23;

-- Node name is ':6676' 
-- Equation name is '_LC1_B23', type is buried 
_LC1_B23 = LCELL( _EQ046);
  _EQ046 =  cs &  _LC1_B23
         #  _LC1_B21 &  _LC8_B23;

-- Node name is '~6677~1' 
-- Equation name is '~6677~1', location is LC7_B21, type is buried.
-- synthesized logic cell 
_LC7_B21 = LCELL( _EQ047);
  _EQ047 = !_LC3_B15 &  _LC6_B18
         #  address3 & !_LC3_B15;

-- Node name is ':6682' 
-- Equation name is '_LC7_B24', type is buried 
_LC7_B24 = LCELL( _EQ048);
  _EQ048 =  cs &  _LC7_B24
         #  _LC1_B18 &  _LC8_B24;

-- Node name is '~6683~1' 
-- Equation name is '~6683~1', location is LC1_B18, type is buried.
-- synthesized logic cell 
_LC1_B18 = LCELL( _EQ049);
  _EQ049 = !cs &  _LC1_B16
         # !cs & !_LC4_B18;

-- Node name is ':6688' 
-- Equation name is '_LC1_B20', type is buried 
_LC1_B20 = LCELL( _EQ050);
  _EQ050 =  cs &  _LC1_B20
         #  _LC5_B20 &  _LC8_B20;

-- Node name is ':6694' 
-- Equation name is '_LC2_B20', type is buried 
_LC2_B20 = LCELL( _EQ051);
  _EQ051 =  cs &  _LC2_B20
         #  _LC2_B21 &  _LC5_B20;

-- Node name is '~6695~1' 
-- Equation name is '~6695~1', location is LC2_B24, type is buried.
-- synthesized logic cell 
_LC2_B24 = LCELL( _EQ052);
  _EQ052 = !_LC1_B15 &  _LC1_B18;

-- Node name is '~6695~2' 
-- Equation name is '~6695~2', location is LC5_B23, type is buried.
-- synthesized logic cell 
_LC5_B23 = LCELL( _EQ053);
  _EQ053 = !_LC2_B18 & !_LC4_B15
         #  address3 & !_LC2_B18;

-- Node name is ':6700' 
-- Equation name is '_LC6_B24', type is buried 
_LC6_B24 = LCELL( _EQ054);
  _EQ054 =  cs &  _LC6_B24
         #  _LC1_B24 &  _LC2_B24;

-- Node name is ':6706' 
-- Equation name is '_LC3_B21', type is buried 
_LC3_B21 = LCELL( _EQ055);
  _EQ055 =  cs &  _LC3_B21
         #  _LC1_B18 &  _LC8_B21;



Project Information                                       d:\xiaoning\rom1.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 19,623K