alu.rpt

用vhdl写的

-- Equation name is '_LC064', type is buried 
_LC064   = LCELL( _EQ025 $  GND);
  _EQ025 =  a4 & !b4 &  _X016 &  _X017
         #  a5 & !b5 &  _X017
         #  a6 & !b6;
  _X016  = EXP(!a5 &  b5);
  _X017  = EXP(!a6 &  b6);

-- Node name is '|LPM_ADD_SUB:236|addcore:adder|g4' from file "addcore.tdf" line 158, column 5
-- Equation name is '_LC063', type is buried 
_LC063   = LCELL( _EQ026 $  GND);
  _EQ026 =  a0 & !b0 &  _X018 &  _X019 &  _X020
         #  a1 & !b1 &  _X018 &  _X019
         #  a2 & !b2 &  _X019
         #  a3 & !b3;
  _X018  = EXP(!a2 &  b2);
  _X019  = EXP(!a3 &  b3);
  _X020  = EXP(!a1 &  b1);

-- Node name is '|LPM_ADD_SUB:236|addcore:adder|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC044', type is buried 
_LC044   = LCELL( _EQ027 $  _EQ028);
  _EQ027 =  a0 & !b0
         #  _X021;
  _X021  = EXP(!a0 &  b0);
  _EQ028 =  _X020 &  _X022;
  _X020  = EXP(!a1 &  b1);
  _X022  = EXP( a1 & !b1);

-- Node name is '|LPM_ADD_SUB:236|addcore:adder|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC056', type is buried 
_LC056   = LCELL( _EQ029 $  _EQ030);
  _EQ029 =  a0 & !b0 &  _X020
         #  a1 & !b1
         #  _X020 &  _X021;
  _X020  = EXP(!a1 &  b1);
  _X021  = EXP(!a0 &  b0);
  _EQ030 =  _X018 &  _X023;
  _X018  = EXP(!a2 &  b2);
  _X023  = EXP( a2 & !b2);

-- Node name is '|LPM_ADD_SUB:236|addcore:adder|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC055', type is buried 
_LC055   = LCELL( _EQ031 $  _EQ032);
  _EQ031 =  a0 & !b0 &  _X018 &  _X020
         #  a1 & !b1 &  _X018
         #  _X018 &  _X020 &  _X021
         #  a2 & !b2;
  _X018  = EXP(!a2 &  b2);
  _X020  = EXP(!a1 &  b1);
  _X021  = EXP(!a0 &  b0);
  _EQ032 =  _X019 &  _X024;
  _X019  = EXP(!a3 &  b3);
  _X024  = EXP( a3 & !b3);

-- Node name is '|LPM_ADD_SUB:236|addcore:adder|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC054', type is buried 
_LC054   = LCELL( _EQ033 $  _EQ034);
  _EQ033 =  _X018 &  _X019 &  _X020 &  _X021
         #  _LC063;
  _X018  = EXP(!a2 &  b2);
  _X019  = EXP(!a3 &  b3);
  _X020  = EXP(!a1 &  b1);
  _X021  = EXP(!a0 &  b0);
  _EQ034 =  _X025 &  _X026;
  _X025  = EXP( a4 & !b4);
  _X026  = EXP(!a4 &  b4);

-- Node name is '|LPM_ADD_SUB:236|addcore:adder|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC051', type is buried 
_LC051   = LCELL( _EQ035 $  _EQ036);
  _EQ035 =  _X018 &  _X019 &  _X020 &  _X021 &  _X026
         #  _LC063 &  _X026
         #  a4 & !b4;
  _X018  = EXP(!a2 &  b2);
  _X019  = EXP(!a3 &  b3);
  _X020  = EXP(!a1 &  b1);
  _X021  = EXP(!a0 &  b0);
  _X026  = EXP(!a4 &  b4);
  _EQ036 =  _X016 &  _X027;
  _X016  = EXP(!a5 &  b5);
  _X027  = EXP( a5 & !b5);

-- Node name is '|LPM_ADD_SUB:236|addcore:adder|result_node6' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC050', type is buried 
_LC050   = LCELL( _EQ037 $  _EQ038);
  _EQ037 =  _X016 &  _X018 &  _X019 &  _X020 &  _X021 &  _X026
         #  _LC063 &  _X016 &  _X026
         #  a4 & !b4 &  _X016
         #  a5 & !b5;
  _X016  = EXP(!a5 &  b5);
  _X018  = EXP(!a2 &  b2);
  _X019  = EXP(!a3 &  b3);
  _X020  = EXP(!a1 &  b1);
  _X021  = EXP(!a0 &  b0);
  _X026  = EXP(!a4 &  b4);
  _EQ038 =  _X017 &  _X028;
  _X017  = EXP(!a6 &  b6);
  _X028  = EXP( a6 & !b6);

-- Node name is '|LPM_ADD_SUB:236|addcore:adder|result_node7' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC049', type is buried 
_LC049   = LCELL( _EQ039 $  _EQ040);
  _EQ039 =  _X016 &  _X017 &  _X018 &  _X019 &  _X020 &  _X021 &  _X026
         #  _LC063 &  _X016 &  _X017 &  _X026
         #  _LC064;
  _X016  = EXP(!a5 &  b5);
  _X017  = EXP(!a6 &  b6);
  _X018  = EXP(!a2 &  b2);
  _X019  = EXP(!a3 &  b3);
  _X020  = EXP(!a1 &  b1);
  _X021  = EXP(!a0 &  b0);
  _X026  = EXP(!a4 &  b4);
  _EQ040 =  _X029 &  _X030;
  _X029  = EXP(!a7 &  b7);
  _X030  = EXP( a7 & !b7);

-- Node name is '|LPM_ADD_SUB:396|addcore:adder|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC036', type is buried 
_LC036   = LCELL( a1 $  a0);

-- Node name is '|LPM_ADD_SUB:396|addcore:adder|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC052', type is buried 
_LC052   = LCELL( a2 $  _EQ041);
  _EQ041 =  a0 &  a1;

-- Node name is '|LPM_ADD_SUB:396|addcore:adder|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC053', type is buried 
_LC053   = LCELL( a3 $  _EQ042);
  _EQ042 =  a0 &  a1 &  a2;

-- Node name is '|LPM_ADD_SUB:396|addcore:adder|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC057', type is buried 
_LC057   = LCELL( a4 $  _EQ043);
  _EQ043 =  a0 &  a1 &  a2 &  a3;

-- Node name is '|LPM_ADD_SUB:396|addcore:adder|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC058', type is buried 
_LC058   = LCELL( a5 $  _EQ044);
  _EQ044 =  a0 &  a1 &  a2 &  a3 &  a4;

-- Node name is '|LPM_ADD_SUB:396|addcore:adder|result_node6' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC062', type is buried 
_LC062   = LCELL( a6 $  _EQ045);
  _EQ045 =  a0 &  a1 &  a2 &  a3 &  a4 &  a5;

-- Node name is '|LPM_ADD_SUB:396|addcore:adder|result_node7' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC061', type is buried 
_LC061   = LCELL( a7 $  _EQ046);
  _EQ046 =  a0 &  a1 &  a2 &  a3 &  a4 &  a5 &  a6;

-- Node name is '~263~1' 
-- Equation name is '~263~1', location is LC001, type is buried.
-- synthesized logic cell 
_LC001   = LCELL( _EQ047 $  VCC);
  _EQ047 =  a5 &  _X017 &  _X031
         # !b5 &  _X017 &  _X031
         # !a7 &  b7
         #  a7 & !b7
         #  a6 & !b6;
  _X017  = EXP(!a6 &  b6);
  _X031  = EXP( _LC018 &  _LC033);

-- Node name is '~275~1' 
-- Equation name is '~275~1', location is LC018, type is buried.
-- synthesized logic cell 
_LC018   = LCELL(!a5 $  b5);

-- Node name is '~276~1' 
-- Equation name is '~276~1', location is LC033, type is buried.
-- synthesized logic cell 
_LC033   = LCELL( _EQ048 $  GND);
  _EQ048 = !a0 &  b0 &  _X022 &  _X023 &  _X024 &  _X025
         # !a1 &  b1 &  _X023 &  _X024 &  _X025
         # !a2 &  b2 &  _X024 &  _X025
         # !a3 &  b3 &  _X025
         # !a4 &  b4;
  _X022  = EXP( a1 & !b1);
  _X023  = EXP( a2 & !b2);
  _X024  = EXP( a3 & !b3);
  _X025  = EXP( a4 & !b4);

-- Node name is '~315~1' 
-- Equation name is '~315~1', location is LC059, type is buried.
-- synthesized logic cell 
_LC059   = LCELL(!b7 $  a7);

-- Node name is '~316~1' 
-- Equation name is '~316~1', location is LC060, type is buried.
-- synthesized logic cell 
_LC060   = LCELL(!b6 $  a6);

-- Node name is '~317~1' 
-- Equation name is '~317~1', location is LC022, type is buried.
-- synthesized logic cell 
_LC022   = LCELL(!b5 $  a5);

-- Node name is '~318~1' 
-- Equation name is '~318~1', location is LC038, type is buried.
-- synthesized logic cell 
_LC038   = LCELL(!b4 $  a4);

-- Node name is '~319~1' 
-- Equation name is '~319~1', location is LC039, type is buried.
-- synthesized logic cell 
_LC039   = LCELL(!b3 $  a3);

-- Node name is '~320~1' 
-- Equation name is '~320~1', location is LC040, type is buried.
-- synthesized logic cell 
_LC040   = LCELL(!b2 $  a2);

-- Node name is '~321~1' 
-- Equation name is '~321~1', location is LC041, type is buried.
-- synthesized logic cell 
_LC041   = LCELL(!b1 $  a1);

-- Node name is '~322~1' 
-- Equation name is '~322~1', location is LC042, type is buried.
-- synthesized logic cell 
_LC042   = LCELL(!b0 $  a0);

-- Node name is '~347~1' 
-- Equation name is '~347~1', location is LC009, type is buried.
-- synthesized logic cell 
_LC009   = LCELL( _EQ049 $  _LC001);
  _EQ049 = !a7 &  b7 & !_LC001;



--     Shareable expanders that are duplicated in multiple LABs:
--    _X017 occurs in LABs A, D
--    _X020 occurs in LABs C, D
--    _X021 occurs in LABs C, D
--    _X023 occurs in LABs C, D
--    _X024 occurs in LABs C, D
--    _X025 occurs in LABs C, D




Project Information                                        d:\xiaoning\alu.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:01
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 4,064K